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STM32F10x Standard Peripherals Library
3.5.0
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STM32F10x Standard Peripherals Library
3.5.0
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00001 00023 /* Define to prevent recursive inclusion -------------------------------------*/ 00024 #ifndef __STM32F10x_TIM_H 00025 #define __STM32F10x_TIM_H 00026 00027 #ifdef __cplusplus 00028 extern "C" { 00029 #endif 00030 00031 /* Includes ------------------------------------------------------------------*/ 00032 #include "stm32f10x.h" 00033 00051 typedef struct 00052 { 00053 uint16_t TIM_Prescaler; 00056 uint16_t TIM_CounterMode; 00059 uint16_t TIM_Period; 00063 uint16_t TIM_ClockDivision; 00066 uint8_t TIM_RepetitionCounter; 00074 } TIM_TimeBaseInitTypeDef; 00075 00080 typedef struct 00081 { 00082 uint16_t TIM_OCMode; 00085 uint16_t TIM_OutputState; 00088 uint16_t TIM_OutputNState; 00092 uint16_t TIM_Pulse; 00095 uint16_t TIM_OCPolarity; 00098 uint16_t TIM_OCNPolarity; 00102 uint16_t TIM_OCIdleState; 00106 uint16_t TIM_OCNIdleState; 00109 } TIM_OCInitTypeDef; 00110 00115 typedef struct 00116 { 00117 00118 uint16_t TIM_Channel; 00121 uint16_t TIM_ICPolarity; 00124 uint16_t TIM_ICSelection; 00127 uint16_t TIM_ICPrescaler; 00130 uint16_t TIM_ICFilter; 00132 } TIM_ICInitTypeDef; 00133 00139 typedef struct 00140 { 00141 00142 uint16_t TIM_OSSRState; 00145 uint16_t TIM_OSSIState; 00148 uint16_t TIM_LOCKLevel; 00151 uint16_t TIM_DeadTime; 00155 uint16_t TIM_Break; 00158 uint16_t TIM_BreakPolarity; 00161 uint16_t TIM_AutomaticOutput; 00163 } TIM_BDTRInitTypeDef; 00164 00169 #define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 00170 ((PERIPH) == TIM2) || \ 00171 ((PERIPH) == TIM3) || \ 00172 ((PERIPH) == TIM4) || \ 00173 ((PERIPH) == TIM5) || \ 00174 ((PERIPH) == TIM6) || \ 00175 ((PERIPH) == TIM7) || \ 00176 ((PERIPH) == TIM8) || \ 00177 ((PERIPH) == TIM9) || \ 00178 ((PERIPH) == TIM10)|| \ 00179 ((PERIPH) == TIM11)|| \ 00180 ((PERIPH) == TIM12)|| \ 00181 ((PERIPH) == TIM13)|| \ 00182 ((PERIPH) == TIM14)|| \ 00183 ((PERIPH) == TIM15)|| \ 00184 ((PERIPH) == TIM16)|| \ 00185 ((PERIPH) == TIM17)) 00186 00187 /* LIST1: TIM 1 and 8 */ 00188 #define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 00189 ((PERIPH) == TIM8)) 00190 00191 /* LIST2: TIM 1, 8, 15 16 and 17 */ 00192 #define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 00193 ((PERIPH) == TIM8) || \ 00194 ((PERIPH) == TIM15)|| \ 00195 ((PERIPH) == TIM16)|| \ 00196 ((PERIPH) == TIM17)) 00197 00198 /* LIST3: TIM 1, 2, 3, 4, 5 and 8 */ 00199 #define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 00200 ((PERIPH) == TIM2) || \ 00201 ((PERIPH) == TIM3) || \ 00202 ((PERIPH) == TIM4) || \ 00203 ((PERIPH) == TIM5) || \ 00204 ((PERIPH) == TIM8)) 00205 00206 /* LIST4: TIM 1, 2, 3, 4, 5, 8, 15, 16 and 17 */ 00207 #define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 00208 ((PERIPH) == TIM2) || \ 00209 ((PERIPH) == TIM3) || \ 00210 ((PERIPH) == TIM4) || \ 00211 ((PERIPH) == TIM5) || \ 00212 ((PERIPH) == TIM8) || \ 00213 ((PERIPH) == TIM15)|| \ 00214 ((PERIPH) == TIM16)|| \ 00215 ((PERIPH) == TIM17)) 00216 00217 /* LIST5: TIM 1, 2, 3, 4, 5, 8 and 15 */ 00218 #define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 00219 ((PERIPH) == TIM2) || \ 00220 ((PERIPH) == TIM3) || \ 00221 ((PERIPH) == TIM4) || \ 00222 ((PERIPH) == TIM5) || \ 00223 ((PERIPH) == TIM8) || \ 00224 ((PERIPH) == TIM15)) 00225 00226 /* LIST6: TIM 1, 2, 3, 4, 5, 8, 9, 12 and 15 */ 00227 #define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 00228 ((PERIPH) == TIM2) || \ 00229 ((PERIPH) == TIM3) || \ 00230 ((PERIPH) == TIM4) || \ 00231 ((PERIPH) == TIM5) || \ 00232 ((PERIPH) == TIM8) || \ 00233 ((PERIPH) == TIM9) || \ 00234 ((PERIPH) == TIM12)|| \ 00235 ((PERIPH) == TIM15)) 00236 00237 /* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 and 15 */ 00238 #define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 00239 ((PERIPH) == TIM2) || \ 00240 ((PERIPH) == TIM3) || \ 00241 ((PERIPH) == TIM4) || \ 00242 ((PERIPH) == TIM5) || \ 00243 ((PERIPH) == TIM6) || \ 00244 ((PERIPH) == TIM7) || \ 00245 ((PERIPH) == TIM8) || \ 00246 ((PERIPH) == TIM9) || \ 00247 ((PERIPH) == TIM12)|| \ 00248 ((PERIPH) == TIM15)) 00249 00250 /* LIST8: TIM 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17 */ 00251 #define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 00252 ((PERIPH) == TIM2) || \ 00253 ((PERIPH) == TIM3) || \ 00254 ((PERIPH) == TIM4) || \ 00255 ((PERIPH) == TIM5) || \ 00256 ((PERIPH) == TIM8) || \ 00257 ((PERIPH) == TIM9) || \ 00258 ((PERIPH) == TIM10)|| \ 00259 ((PERIPH) == TIM11)|| \ 00260 ((PERIPH) == TIM12)|| \ 00261 ((PERIPH) == TIM13)|| \ 00262 ((PERIPH) == TIM14)|| \ 00263 ((PERIPH) == TIM15)|| \ 00264 ((PERIPH) == TIM16)|| \ 00265 ((PERIPH) == TIM17)) 00266 00267 /* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8, 15, 16, and 17 */ 00268 #define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 00269 ((PERIPH) == TIM2) || \ 00270 ((PERIPH) == TIM3) || \ 00271 ((PERIPH) == TIM4) || \ 00272 ((PERIPH) == TIM5) || \ 00273 ((PERIPH) == TIM6) || \ 00274 ((PERIPH) == TIM7) || \ 00275 ((PERIPH) == TIM8) || \ 00276 ((PERIPH) == TIM15)|| \ 00277 ((PERIPH) == TIM16)|| \ 00278 ((PERIPH) == TIM17)) 00279 00288 #define TIM_OCMode_Timing ((uint16_t)0x0000) 00289 #define TIM_OCMode_Active ((uint16_t)0x0010) 00290 #define TIM_OCMode_Inactive ((uint16_t)0x0020) 00291 #define TIM_OCMode_Toggle ((uint16_t)0x0030) 00292 #define TIM_OCMode_PWM1 ((uint16_t)0x0060) 00293 #define TIM_OCMode_PWM2 ((uint16_t)0x0070) 00294 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ 00295 ((MODE) == TIM_OCMode_Active) || \ 00296 ((MODE) == TIM_OCMode_Inactive) || \ 00297 ((MODE) == TIM_OCMode_Toggle)|| \ 00298 ((MODE) == TIM_OCMode_PWM1) || \ 00299 ((MODE) == TIM_OCMode_PWM2)) 00300 #define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ 00301 ((MODE) == TIM_OCMode_Active) || \ 00302 ((MODE) == TIM_OCMode_Inactive) || \ 00303 ((MODE) == TIM_OCMode_Toggle)|| \ 00304 ((MODE) == TIM_OCMode_PWM1) || \ 00305 ((MODE) == TIM_OCMode_PWM2) || \ 00306 ((MODE) == TIM_ForcedAction_Active) || \ 00307 ((MODE) == TIM_ForcedAction_InActive)) 00308 00316 #define TIM_OPMode_Single ((uint16_t)0x0008) 00317 #define TIM_OPMode_Repetitive ((uint16_t)0x0000) 00318 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ 00319 ((MODE) == TIM_OPMode_Repetitive)) 00320 00328 #define TIM_Channel_1 ((uint16_t)0x0000) 00329 #define TIM_Channel_2 ((uint16_t)0x0004) 00330 #define TIM_Channel_3 ((uint16_t)0x0008) 00331 #define TIM_Channel_4 ((uint16_t)0x000C) 00332 #define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ 00333 ((CHANNEL) == TIM_Channel_2) || \ 00334 ((CHANNEL) == TIM_Channel_3) || \ 00335 ((CHANNEL) == TIM_Channel_4)) 00336 #define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ 00337 ((CHANNEL) == TIM_Channel_2)) 00338 #define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ 00339 ((CHANNEL) == TIM_Channel_2) || \ 00340 ((CHANNEL) == TIM_Channel_3)) 00341 00349 #define TIM_CKD_DIV1 ((uint16_t)0x0000) 00350 #define TIM_CKD_DIV2 ((uint16_t)0x0100) 00351 #define TIM_CKD_DIV4 ((uint16_t)0x0200) 00352 #define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ 00353 ((DIV) == TIM_CKD_DIV2) || \ 00354 ((DIV) == TIM_CKD_DIV4)) 00355 00363 #define TIM_CounterMode_Up ((uint16_t)0x0000) 00364 #define TIM_CounterMode_Down ((uint16_t)0x0010) 00365 #define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) 00366 #define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) 00367 #define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) 00368 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ 00369 ((MODE) == TIM_CounterMode_Down) || \ 00370 ((MODE) == TIM_CounterMode_CenterAligned1) || \ 00371 ((MODE) == TIM_CounterMode_CenterAligned2) || \ 00372 ((MODE) == TIM_CounterMode_CenterAligned3)) 00373 00381 #define TIM_OCPolarity_High ((uint16_t)0x0000) 00382 #define TIM_OCPolarity_Low ((uint16_t)0x0002) 00383 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ 00384 ((POLARITY) == TIM_OCPolarity_Low)) 00385 00393 #define TIM_OCNPolarity_High ((uint16_t)0x0000) 00394 #define TIM_OCNPolarity_Low ((uint16_t)0x0008) 00395 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ 00396 ((POLARITY) == TIM_OCNPolarity_Low)) 00397 00405 #define TIM_OutputState_Disable ((uint16_t)0x0000) 00406 #define TIM_OutputState_Enable ((uint16_t)0x0001) 00407 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ 00408 ((STATE) == TIM_OutputState_Enable)) 00409 00417 #define TIM_OutputNState_Disable ((uint16_t)0x0000) 00418 #define TIM_OutputNState_Enable ((uint16_t)0x0004) 00419 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ 00420 ((STATE) == TIM_OutputNState_Enable)) 00421 00429 #define TIM_CCx_Enable ((uint16_t)0x0001) 00430 #define TIM_CCx_Disable ((uint16_t)0x0000) 00431 #define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ 00432 ((CCX) == TIM_CCx_Disable)) 00433 00441 #define TIM_CCxN_Enable ((uint16_t)0x0004) 00442 #define TIM_CCxN_Disable ((uint16_t)0x0000) 00443 #define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ 00444 ((CCXN) == TIM_CCxN_Disable)) 00445 00453 #define TIM_Break_Enable ((uint16_t)0x1000) 00454 #define TIM_Break_Disable ((uint16_t)0x0000) 00455 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ 00456 ((STATE) == TIM_Break_Disable)) 00457 00465 #define TIM_BreakPolarity_Low ((uint16_t)0x0000) 00466 #define TIM_BreakPolarity_High ((uint16_t)0x2000) 00467 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ 00468 ((POLARITY) == TIM_BreakPolarity_High)) 00469 00477 #define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) 00478 #define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) 00479 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ 00480 ((STATE) == TIM_AutomaticOutput_Disable)) 00481 00489 #define TIM_LOCKLevel_OFF ((uint16_t)0x0000) 00490 #define TIM_LOCKLevel_1 ((uint16_t)0x0100) 00491 #define TIM_LOCKLevel_2 ((uint16_t)0x0200) 00492 #define TIM_LOCKLevel_3 ((uint16_t)0x0300) 00493 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ 00494 ((LEVEL) == TIM_LOCKLevel_1) || \ 00495 ((LEVEL) == TIM_LOCKLevel_2) || \ 00496 ((LEVEL) == TIM_LOCKLevel_3)) 00497 00505 #define TIM_OSSIState_Enable ((uint16_t)0x0400) 00506 #define TIM_OSSIState_Disable ((uint16_t)0x0000) 00507 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ 00508 ((STATE) == TIM_OSSIState_Disable)) 00509 00517 #define TIM_OSSRState_Enable ((uint16_t)0x0800) 00518 #define TIM_OSSRState_Disable ((uint16_t)0x0000) 00519 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ 00520 ((STATE) == TIM_OSSRState_Disable)) 00521 00529 #define TIM_OCIdleState_Set ((uint16_t)0x0100) 00530 #define TIM_OCIdleState_Reset ((uint16_t)0x0000) 00531 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ 00532 ((STATE) == TIM_OCIdleState_Reset)) 00533 00541 #define TIM_OCNIdleState_Set ((uint16_t)0x0200) 00542 #define TIM_OCNIdleState_Reset ((uint16_t)0x0000) 00543 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ 00544 ((STATE) == TIM_OCNIdleState_Reset)) 00545 00553 #define TIM_ICPolarity_Rising ((uint16_t)0x0000) 00554 #define TIM_ICPolarity_Falling ((uint16_t)0x0002) 00555 #define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) 00556 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ 00557 ((POLARITY) == TIM_ICPolarity_Falling)) 00558 #define IS_TIM_IC_POLARITY_LITE(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ 00559 ((POLARITY) == TIM_ICPolarity_Falling)|| \ 00560 ((POLARITY) == TIM_ICPolarity_BothEdge)) 00561 00569 #define TIM_ICSelection_DirectTI ((uint16_t)0x0001) 00571 #define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) 00573 #define TIM_ICSelection_TRC ((uint16_t)0x0003) 00574 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ 00575 ((SELECTION) == TIM_ICSelection_IndirectTI) || \ 00576 ((SELECTION) == TIM_ICSelection_TRC)) 00577 00585 #define TIM_ICPSC_DIV1 ((uint16_t)0x0000) 00586 #define TIM_ICPSC_DIV2 ((uint16_t)0x0004) 00587 #define TIM_ICPSC_DIV4 ((uint16_t)0x0008) 00588 #define TIM_ICPSC_DIV8 ((uint16_t)0x000C) 00589 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ 00590 ((PRESCALER) == TIM_ICPSC_DIV2) || \ 00591 ((PRESCALER) == TIM_ICPSC_DIV4) || \ 00592 ((PRESCALER) == TIM_ICPSC_DIV8)) 00593 00601 #define TIM_IT_Update ((uint16_t)0x0001) 00602 #define TIM_IT_CC1 ((uint16_t)0x0002) 00603 #define TIM_IT_CC2 ((uint16_t)0x0004) 00604 #define TIM_IT_CC3 ((uint16_t)0x0008) 00605 #define TIM_IT_CC4 ((uint16_t)0x0010) 00606 #define TIM_IT_COM ((uint16_t)0x0020) 00607 #define TIM_IT_Trigger ((uint16_t)0x0040) 00608 #define TIM_IT_Break ((uint16_t)0x0080) 00609 #define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) 00610 00611 #define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ 00612 ((IT) == TIM_IT_CC1) || \ 00613 ((IT) == TIM_IT_CC2) || \ 00614 ((IT) == TIM_IT_CC3) || \ 00615 ((IT) == TIM_IT_CC4) || \ 00616 ((IT) == TIM_IT_COM) || \ 00617 ((IT) == TIM_IT_Trigger) || \ 00618 ((IT) == TIM_IT_Break)) 00619 00627 #define TIM_DMABase_CR1 ((uint16_t)0x0000) 00628 #define TIM_DMABase_CR2 ((uint16_t)0x0001) 00629 #define TIM_DMABase_SMCR ((uint16_t)0x0002) 00630 #define TIM_DMABase_DIER ((uint16_t)0x0003) 00631 #define TIM_DMABase_SR ((uint16_t)0x0004) 00632 #define TIM_DMABase_EGR ((uint16_t)0x0005) 00633 #define TIM_DMABase_CCMR1 ((uint16_t)0x0006) 00634 #define TIM_DMABase_CCMR2 ((uint16_t)0x0007) 00635 #define TIM_DMABase_CCER ((uint16_t)0x0008) 00636 #define TIM_DMABase_CNT ((uint16_t)0x0009) 00637 #define TIM_DMABase_PSC ((uint16_t)0x000A) 00638 #define TIM_DMABase_ARR ((uint16_t)0x000B) 00639 #define TIM_DMABase_RCR ((uint16_t)0x000C) 00640 #define TIM_DMABase_CCR1 ((uint16_t)0x000D) 00641 #define TIM_DMABase_CCR2 ((uint16_t)0x000E) 00642 #define TIM_DMABase_CCR3 ((uint16_t)0x000F) 00643 #define TIM_DMABase_CCR4 ((uint16_t)0x0010) 00644 #define TIM_DMABase_BDTR ((uint16_t)0x0011) 00645 #define TIM_DMABase_DCR ((uint16_t)0x0012) 00646 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ 00647 ((BASE) == TIM_DMABase_CR2) || \ 00648 ((BASE) == TIM_DMABase_SMCR) || \ 00649 ((BASE) == TIM_DMABase_DIER) || \ 00650 ((BASE) == TIM_DMABase_SR) || \ 00651 ((BASE) == TIM_DMABase_EGR) || \ 00652 ((BASE) == TIM_DMABase_CCMR1) || \ 00653 ((BASE) == TIM_DMABase_CCMR2) || \ 00654 ((BASE) == TIM_DMABase_CCER) || \ 00655 ((BASE) == TIM_DMABase_CNT) || \ 00656 ((BASE) == TIM_DMABase_PSC) || \ 00657 ((BASE) == TIM_DMABase_ARR) || \ 00658 ((BASE) == TIM_DMABase_RCR) || \ 00659 ((BASE) == TIM_DMABase_CCR1) || \ 00660 ((BASE) == TIM_DMABase_CCR2) || \ 00661 ((BASE) == TIM_DMABase_CCR3) || \ 00662 ((BASE) == TIM_DMABase_CCR4) || \ 00663 ((BASE) == TIM_DMABase_BDTR) || \ 00664 ((BASE) == TIM_DMABase_DCR)) 00665 00673 #define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) 00674 #define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) 00675 #define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) 00676 #define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) 00677 #define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) 00678 #define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) 00679 #define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) 00680 #define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) 00681 #define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) 00682 #define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) 00683 #define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) 00684 #define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) 00685 #define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) 00686 #define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) 00687 #define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) 00688 #define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) 00689 #define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) 00690 #define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) 00691 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ 00692 ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ 00693 ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ 00694 ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ 00695 ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ 00696 ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ 00697 ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ 00698 ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ 00699 ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ 00700 ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ 00701 ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ 00702 ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ 00703 ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ 00704 ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ 00705 ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ 00706 ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ 00707 ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ 00708 ((LENGTH) == TIM_DMABurstLength_18Transfers)) 00709 00717 #define TIM_DMA_Update ((uint16_t)0x0100) 00718 #define TIM_DMA_CC1 ((uint16_t)0x0200) 00719 #define TIM_DMA_CC2 ((uint16_t)0x0400) 00720 #define TIM_DMA_CC3 ((uint16_t)0x0800) 00721 #define TIM_DMA_CC4 ((uint16_t)0x1000) 00722 #define TIM_DMA_COM ((uint16_t)0x2000) 00723 #define TIM_DMA_Trigger ((uint16_t)0x4000) 00724 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) 00725 00734 #define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) 00735 #define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) 00736 #define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) 00737 #define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) 00738 #define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ 00739 ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ 00740 ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ 00741 ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) 00742 00750 #define TIM_TS_ITR0 ((uint16_t)0x0000) 00751 #define TIM_TS_ITR1 ((uint16_t)0x0010) 00752 #define TIM_TS_ITR2 ((uint16_t)0x0020) 00753 #define TIM_TS_ITR3 ((uint16_t)0x0030) 00754 #define TIM_TS_TI1F_ED ((uint16_t)0x0040) 00755 #define TIM_TS_TI1FP1 ((uint16_t)0x0050) 00756 #define TIM_TS_TI2FP2 ((uint16_t)0x0060) 00757 #define TIM_TS_ETRF ((uint16_t)0x0070) 00758 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ 00759 ((SELECTION) == TIM_TS_ITR1) || \ 00760 ((SELECTION) == TIM_TS_ITR2) || \ 00761 ((SELECTION) == TIM_TS_ITR3) || \ 00762 ((SELECTION) == TIM_TS_TI1F_ED) || \ 00763 ((SELECTION) == TIM_TS_TI1FP1) || \ 00764 ((SELECTION) == TIM_TS_TI2FP2) || \ 00765 ((SELECTION) == TIM_TS_ETRF)) 00766 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ 00767 ((SELECTION) == TIM_TS_ITR1) || \ 00768 ((SELECTION) == TIM_TS_ITR2) || \ 00769 ((SELECTION) == TIM_TS_ITR3)) 00770 00778 #define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) 00779 #define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) 00780 #define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) 00781 #define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \ 00782 ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \ 00783 ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED)) 00784 00791 #define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) 00792 #define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) 00793 #define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ 00794 ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) 00795 00803 #define TIM_PSCReloadMode_Update ((uint16_t)0x0000) 00804 #define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) 00805 #define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ 00806 ((RELOAD) == TIM_PSCReloadMode_Immediate)) 00807 00815 #define TIM_ForcedAction_Active ((uint16_t)0x0050) 00816 #define TIM_ForcedAction_InActive ((uint16_t)0x0040) 00817 #define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ 00818 ((ACTION) == TIM_ForcedAction_InActive)) 00819 00827 #define TIM_EncoderMode_TI1 ((uint16_t)0x0001) 00828 #define TIM_EncoderMode_TI2 ((uint16_t)0x0002) 00829 #define TIM_EncoderMode_TI12 ((uint16_t)0x0003) 00830 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ 00831 ((MODE) == TIM_EncoderMode_TI2) || \ 00832 ((MODE) == TIM_EncoderMode_TI12)) 00833 00842 #define TIM_EventSource_Update ((uint16_t)0x0001) 00843 #define TIM_EventSource_CC1 ((uint16_t)0x0002) 00844 #define TIM_EventSource_CC2 ((uint16_t)0x0004) 00845 #define TIM_EventSource_CC3 ((uint16_t)0x0008) 00846 #define TIM_EventSource_CC4 ((uint16_t)0x0010) 00847 #define TIM_EventSource_COM ((uint16_t)0x0020) 00848 #define TIM_EventSource_Trigger ((uint16_t)0x0040) 00849 #define TIM_EventSource_Break ((uint16_t)0x0080) 00850 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) 00851 00860 #define TIM_UpdateSource_Global ((uint16_t)0x0000) 00863 #define TIM_UpdateSource_Regular ((uint16_t)0x0001) 00864 #define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ 00865 ((SOURCE) == TIM_UpdateSource_Regular)) 00866 00874 #define TIM_OCPreload_Enable ((uint16_t)0x0008) 00875 #define TIM_OCPreload_Disable ((uint16_t)0x0000) 00876 #define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ 00877 ((STATE) == TIM_OCPreload_Disable)) 00878 00886 #define TIM_OCFast_Enable ((uint16_t)0x0004) 00887 #define TIM_OCFast_Disable ((uint16_t)0x0000) 00888 #define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ 00889 ((STATE) == TIM_OCFast_Disable)) 00890 00899 #define TIM_OCClear_Enable ((uint16_t)0x0080) 00900 #define TIM_OCClear_Disable ((uint16_t)0x0000) 00901 #define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ 00902 ((STATE) == TIM_OCClear_Disable)) 00903 00911 #define TIM_TRGOSource_Reset ((uint16_t)0x0000) 00912 #define TIM_TRGOSource_Enable ((uint16_t)0x0010) 00913 #define TIM_TRGOSource_Update ((uint16_t)0x0020) 00914 #define TIM_TRGOSource_OC1 ((uint16_t)0x0030) 00915 #define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) 00916 #define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) 00917 #define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) 00918 #define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) 00919 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ 00920 ((SOURCE) == TIM_TRGOSource_Enable) || \ 00921 ((SOURCE) == TIM_TRGOSource_Update) || \ 00922 ((SOURCE) == TIM_TRGOSource_OC1) || \ 00923 ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ 00924 ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ 00925 ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ 00926 ((SOURCE) == TIM_TRGOSource_OC4Ref)) 00927 00935 #define TIM_SlaveMode_Reset ((uint16_t)0x0004) 00936 #define TIM_SlaveMode_Gated ((uint16_t)0x0005) 00937 #define TIM_SlaveMode_Trigger ((uint16_t)0x0006) 00938 #define TIM_SlaveMode_External1 ((uint16_t)0x0007) 00939 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ 00940 ((MODE) == TIM_SlaveMode_Gated) || \ 00941 ((MODE) == TIM_SlaveMode_Trigger) || \ 00942 ((MODE) == TIM_SlaveMode_External1)) 00943 00951 #define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) 00952 #define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) 00953 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ 00954 ((STATE) == TIM_MasterSlaveMode_Disable)) 00955 00963 #define TIM_FLAG_Update ((uint16_t)0x0001) 00964 #define TIM_FLAG_CC1 ((uint16_t)0x0002) 00965 #define TIM_FLAG_CC2 ((uint16_t)0x0004) 00966 #define TIM_FLAG_CC3 ((uint16_t)0x0008) 00967 #define TIM_FLAG_CC4 ((uint16_t)0x0010) 00968 #define TIM_FLAG_COM ((uint16_t)0x0020) 00969 #define TIM_FLAG_Trigger ((uint16_t)0x0040) 00970 #define TIM_FLAG_Break ((uint16_t)0x0080) 00971 #define TIM_FLAG_CC1OF ((uint16_t)0x0200) 00972 #define TIM_FLAG_CC2OF ((uint16_t)0x0400) 00973 #define TIM_FLAG_CC3OF ((uint16_t)0x0800) 00974 #define TIM_FLAG_CC4OF ((uint16_t)0x1000) 00975 #define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ 00976 ((FLAG) == TIM_FLAG_CC1) || \ 00977 ((FLAG) == TIM_FLAG_CC2) || \ 00978 ((FLAG) == TIM_FLAG_CC3) || \ 00979 ((FLAG) == TIM_FLAG_CC4) || \ 00980 ((FLAG) == TIM_FLAG_COM) || \ 00981 ((FLAG) == TIM_FLAG_Trigger) || \ 00982 ((FLAG) == TIM_FLAG_Break) || \ 00983 ((FLAG) == TIM_FLAG_CC1OF) || \ 00984 ((FLAG) == TIM_FLAG_CC2OF) || \ 00985 ((FLAG) == TIM_FLAG_CC3OF) || \ 00986 ((FLAG) == TIM_FLAG_CC4OF)) 00987 00988 00989 #define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) 00990 00998 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) 00999 01007 #define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) 01008 01016 #define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer 01017 #define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers 01018 #define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers 01019 #define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers 01020 #define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers 01021 #define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers 01022 #define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers 01023 #define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers 01024 #define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers 01025 #define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers 01026 #define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers 01027 #define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers 01028 #define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers 01029 #define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers 01030 #define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers 01031 #define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers 01032 #define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers 01033 #define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers 01034 01054 void TIM_DeInit(TIM_TypeDef* TIMx); 01055 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); 01056 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); 01057 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); 01058 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); 01059 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); 01060 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); 01061 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); 01062 void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); 01063 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); 01064 void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); 01065 void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); 01066 void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); 01067 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); 01068 void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); 01069 void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); 01070 void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); 01071 void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); 01072 void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); 01073 void TIM_InternalClockConfig(TIM_TypeDef* TIMx); 01074 void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); 01075 void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, 01076 uint16_t TIM_ICPolarity, uint16_t ICFilter); 01077 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, 01078 uint16_t ExtTRGFilter); 01079 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, 01080 uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); 01081 void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, 01082 uint16_t ExtTRGFilter); 01083 void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); 01084 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); 01085 void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); 01086 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, 01087 uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); 01088 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); 01089 void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); 01090 void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); 01091 void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); 01092 void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); 01093 void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); 01094 void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); 01095 void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); 01096 void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); 01097 void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); 01098 void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); 01099 void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); 01100 void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); 01101 void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); 01102 void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); 01103 void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); 01104 void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); 01105 void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); 01106 void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); 01107 void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); 01108 void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); 01109 void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); 01110 void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); 01111 void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); 01112 void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); 01113 void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); 01114 void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); 01115 void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); 01116 void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); 01117 void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); 01118 void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); 01119 void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); 01120 void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); 01121 void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); 01122 void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); 01123 void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); 01124 void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); 01125 void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter); 01126 void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload); 01127 void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1); 01128 void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2); 01129 void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3); 01130 void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4); 01131 void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); 01132 void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); 01133 void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); 01134 void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); 01135 void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); 01136 uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx); 01137 uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx); 01138 uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx); 01139 uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx); 01140 uint16_t TIM_GetCounter(TIM_TypeDef* TIMx); 01141 uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); 01142 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); 01143 void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); 01144 ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); 01145 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); 01146 01147 #ifdef __cplusplus 01148 } 01149 #endif 01150 01151 #endif /*__STM32F10x_TIM_H */ 01152 01164 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
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