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STM32F10x Standard Peripherals Library
3.5.0
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STM32F10x Standard Peripherals Library
3.5.0
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00001 00023 /* Define to prevent recursive inclusion -------------------------------------*/ 00024 #ifndef __STM32F10x_DMA_H 00025 #define __STM32F10x_DMA_H 00026 00027 #ifdef __cplusplus 00028 extern "C" { 00029 #endif 00030 00031 /* Includes ------------------------------------------------------------------*/ 00032 #include "stm32f10x.h" 00033 00050 typedef struct 00051 { 00052 uint32_t DMA_PeripheralBaseAddr; 00054 uint32_t DMA_MemoryBaseAddr; 00056 uint32_t DMA_DIR; 00059 uint32_t DMA_BufferSize; 00063 uint32_t DMA_PeripheralInc; 00066 uint32_t DMA_MemoryInc; 00069 uint32_t DMA_PeripheralDataSize; 00072 uint32_t DMA_MemoryDataSize; 00075 uint32_t DMA_Mode; 00080 uint32_t DMA_Priority; 00083 uint32_t DMA_M2M; 00085 }DMA_InitTypeDef; 00086 00095 #define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \ 00096 ((PERIPH) == DMA1_Channel2) || \ 00097 ((PERIPH) == DMA1_Channel3) || \ 00098 ((PERIPH) == DMA1_Channel4) || \ 00099 ((PERIPH) == DMA1_Channel5) || \ 00100 ((PERIPH) == DMA1_Channel6) || \ 00101 ((PERIPH) == DMA1_Channel7) || \ 00102 ((PERIPH) == DMA2_Channel1) || \ 00103 ((PERIPH) == DMA2_Channel2) || \ 00104 ((PERIPH) == DMA2_Channel3) || \ 00105 ((PERIPH) == DMA2_Channel4) || \ 00106 ((PERIPH) == DMA2_Channel5)) 00107 00112 #define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) 00113 #define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) 00114 #define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \ 00115 ((DIR) == DMA_DIR_PeripheralSRC)) 00116 00124 #define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) 00125 #define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) 00126 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ 00127 ((STATE) == DMA_PeripheralInc_Disable)) 00128 00136 #define DMA_MemoryInc_Enable ((uint32_t)0x00000080) 00137 #define DMA_MemoryInc_Disable ((uint32_t)0x00000000) 00138 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ 00139 ((STATE) == DMA_MemoryInc_Disable)) 00140 00148 #define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) 00149 #define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) 00150 #define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) 00151 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ 00152 ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ 00153 ((SIZE) == DMA_PeripheralDataSize_Word)) 00154 00162 #define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) 00163 #define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) 00164 #define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) 00165 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ 00166 ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ 00167 ((SIZE) == DMA_MemoryDataSize_Word)) 00168 00176 #define DMA_Mode_Circular ((uint32_t)0x00000020) 00177 #define DMA_Mode_Normal ((uint32_t)0x00000000) 00178 #define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal)) 00179 00187 #define DMA_Priority_VeryHigh ((uint32_t)0x00003000) 00188 #define DMA_Priority_High ((uint32_t)0x00002000) 00189 #define DMA_Priority_Medium ((uint32_t)0x00001000) 00190 #define DMA_Priority_Low ((uint32_t)0x00000000) 00191 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \ 00192 ((PRIORITY) == DMA_Priority_High) || \ 00193 ((PRIORITY) == DMA_Priority_Medium) || \ 00194 ((PRIORITY) == DMA_Priority_Low)) 00195 00203 #define DMA_M2M_Enable ((uint32_t)0x00004000) 00204 #define DMA_M2M_Disable ((uint32_t)0x00000000) 00205 #define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable)) 00206 00215 #define DMA_IT_TC ((uint32_t)0x00000002) 00216 #define DMA_IT_HT ((uint32_t)0x00000004) 00217 #define DMA_IT_TE ((uint32_t)0x00000008) 00218 #define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) 00219 00220 #define DMA1_IT_GL1 ((uint32_t)0x00000001) 00221 #define DMA1_IT_TC1 ((uint32_t)0x00000002) 00222 #define DMA1_IT_HT1 ((uint32_t)0x00000004) 00223 #define DMA1_IT_TE1 ((uint32_t)0x00000008) 00224 #define DMA1_IT_GL2 ((uint32_t)0x00000010) 00225 #define DMA1_IT_TC2 ((uint32_t)0x00000020) 00226 #define DMA1_IT_HT2 ((uint32_t)0x00000040) 00227 #define DMA1_IT_TE2 ((uint32_t)0x00000080) 00228 #define DMA1_IT_GL3 ((uint32_t)0x00000100) 00229 #define DMA1_IT_TC3 ((uint32_t)0x00000200) 00230 #define DMA1_IT_HT3 ((uint32_t)0x00000400) 00231 #define DMA1_IT_TE3 ((uint32_t)0x00000800) 00232 #define DMA1_IT_GL4 ((uint32_t)0x00001000) 00233 #define DMA1_IT_TC4 ((uint32_t)0x00002000) 00234 #define DMA1_IT_HT4 ((uint32_t)0x00004000) 00235 #define DMA1_IT_TE4 ((uint32_t)0x00008000) 00236 #define DMA1_IT_GL5 ((uint32_t)0x00010000) 00237 #define DMA1_IT_TC5 ((uint32_t)0x00020000) 00238 #define DMA1_IT_HT5 ((uint32_t)0x00040000) 00239 #define DMA1_IT_TE5 ((uint32_t)0x00080000) 00240 #define DMA1_IT_GL6 ((uint32_t)0x00100000) 00241 #define DMA1_IT_TC6 ((uint32_t)0x00200000) 00242 #define DMA1_IT_HT6 ((uint32_t)0x00400000) 00243 #define DMA1_IT_TE6 ((uint32_t)0x00800000) 00244 #define DMA1_IT_GL7 ((uint32_t)0x01000000) 00245 #define DMA1_IT_TC7 ((uint32_t)0x02000000) 00246 #define DMA1_IT_HT7 ((uint32_t)0x04000000) 00247 #define DMA1_IT_TE7 ((uint32_t)0x08000000) 00248 00249 #define DMA2_IT_GL1 ((uint32_t)0x10000001) 00250 #define DMA2_IT_TC1 ((uint32_t)0x10000002) 00251 #define DMA2_IT_HT1 ((uint32_t)0x10000004) 00252 #define DMA2_IT_TE1 ((uint32_t)0x10000008) 00253 #define DMA2_IT_GL2 ((uint32_t)0x10000010) 00254 #define DMA2_IT_TC2 ((uint32_t)0x10000020) 00255 #define DMA2_IT_HT2 ((uint32_t)0x10000040) 00256 #define DMA2_IT_TE2 ((uint32_t)0x10000080) 00257 #define DMA2_IT_GL3 ((uint32_t)0x10000100) 00258 #define DMA2_IT_TC3 ((uint32_t)0x10000200) 00259 #define DMA2_IT_HT3 ((uint32_t)0x10000400) 00260 #define DMA2_IT_TE3 ((uint32_t)0x10000800) 00261 #define DMA2_IT_GL4 ((uint32_t)0x10001000) 00262 #define DMA2_IT_TC4 ((uint32_t)0x10002000) 00263 #define DMA2_IT_HT4 ((uint32_t)0x10004000) 00264 #define DMA2_IT_TE4 ((uint32_t)0x10008000) 00265 #define DMA2_IT_GL5 ((uint32_t)0x10010000) 00266 #define DMA2_IT_TC5 ((uint32_t)0x10020000) 00267 #define DMA2_IT_HT5 ((uint32_t)0x10040000) 00268 #define DMA2_IT_TE5 ((uint32_t)0x10080000) 00269 00270 #define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00)) 00271 00272 #define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \ 00273 ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \ 00274 ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \ 00275 ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \ 00276 ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \ 00277 ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \ 00278 ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \ 00279 ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \ 00280 ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \ 00281 ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \ 00282 ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \ 00283 ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \ 00284 ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \ 00285 ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \ 00286 ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \ 00287 ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \ 00288 ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \ 00289 ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \ 00290 ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \ 00291 ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \ 00292 ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \ 00293 ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \ 00294 ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \ 00295 ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5)) 00296 00304 #define DMA1_FLAG_GL1 ((uint32_t)0x00000001) 00305 #define DMA1_FLAG_TC1 ((uint32_t)0x00000002) 00306 #define DMA1_FLAG_HT1 ((uint32_t)0x00000004) 00307 #define DMA1_FLAG_TE1 ((uint32_t)0x00000008) 00308 #define DMA1_FLAG_GL2 ((uint32_t)0x00000010) 00309 #define DMA1_FLAG_TC2 ((uint32_t)0x00000020) 00310 #define DMA1_FLAG_HT2 ((uint32_t)0x00000040) 00311 #define DMA1_FLAG_TE2 ((uint32_t)0x00000080) 00312 #define DMA1_FLAG_GL3 ((uint32_t)0x00000100) 00313 #define DMA1_FLAG_TC3 ((uint32_t)0x00000200) 00314 #define DMA1_FLAG_HT3 ((uint32_t)0x00000400) 00315 #define DMA1_FLAG_TE3 ((uint32_t)0x00000800) 00316 #define DMA1_FLAG_GL4 ((uint32_t)0x00001000) 00317 #define DMA1_FLAG_TC4 ((uint32_t)0x00002000) 00318 #define DMA1_FLAG_HT4 ((uint32_t)0x00004000) 00319 #define DMA1_FLAG_TE4 ((uint32_t)0x00008000) 00320 #define DMA1_FLAG_GL5 ((uint32_t)0x00010000) 00321 #define DMA1_FLAG_TC5 ((uint32_t)0x00020000) 00322 #define DMA1_FLAG_HT5 ((uint32_t)0x00040000) 00323 #define DMA1_FLAG_TE5 ((uint32_t)0x00080000) 00324 #define DMA1_FLAG_GL6 ((uint32_t)0x00100000) 00325 #define DMA1_FLAG_TC6 ((uint32_t)0x00200000) 00326 #define DMA1_FLAG_HT6 ((uint32_t)0x00400000) 00327 #define DMA1_FLAG_TE6 ((uint32_t)0x00800000) 00328 #define DMA1_FLAG_GL7 ((uint32_t)0x01000000) 00329 #define DMA1_FLAG_TC7 ((uint32_t)0x02000000) 00330 #define DMA1_FLAG_HT7 ((uint32_t)0x04000000) 00331 #define DMA1_FLAG_TE7 ((uint32_t)0x08000000) 00332 00333 #define DMA2_FLAG_GL1 ((uint32_t)0x10000001) 00334 #define DMA2_FLAG_TC1 ((uint32_t)0x10000002) 00335 #define DMA2_FLAG_HT1 ((uint32_t)0x10000004) 00336 #define DMA2_FLAG_TE1 ((uint32_t)0x10000008) 00337 #define DMA2_FLAG_GL2 ((uint32_t)0x10000010) 00338 #define DMA2_FLAG_TC2 ((uint32_t)0x10000020) 00339 #define DMA2_FLAG_HT2 ((uint32_t)0x10000040) 00340 #define DMA2_FLAG_TE2 ((uint32_t)0x10000080) 00341 #define DMA2_FLAG_GL3 ((uint32_t)0x10000100) 00342 #define DMA2_FLAG_TC3 ((uint32_t)0x10000200) 00343 #define DMA2_FLAG_HT3 ((uint32_t)0x10000400) 00344 #define DMA2_FLAG_TE3 ((uint32_t)0x10000800) 00345 #define DMA2_FLAG_GL4 ((uint32_t)0x10001000) 00346 #define DMA2_FLAG_TC4 ((uint32_t)0x10002000) 00347 #define DMA2_FLAG_HT4 ((uint32_t)0x10004000) 00348 #define DMA2_FLAG_TE4 ((uint32_t)0x10008000) 00349 #define DMA2_FLAG_GL5 ((uint32_t)0x10010000) 00350 #define DMA2_FLAG_TC5 ((uint32_t)0x10020000) 00351 #define DMA2_FLAG_HT5 ((uint32_t)0x10040000) 00352 #define DMA2_FLAG_TE5 ((uint32_t)0x10080000) 00353 00354 #define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00)) 00355 00356 #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \ 00357 ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \ 00358 ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \ 00359 ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \ 00360 ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \ 00361 ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \ 00362 ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \ 00363 ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \ 00364 ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \ 00365 ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \ 00366 ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \ 00367 ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \ 00368 ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \ 00369 ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \ 00370 ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \ 00371 ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \ 00372 ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \ 00373 ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \ 00374 ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \ 00375 ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \ 00376 ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \ 00377 ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \ 00378 ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \ 00379 ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5)) 00380 00388 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) 00389 00410 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); 00411 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); 00412 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); 00413 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); 00414 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); 00415 void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); 00416 uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); 00417 FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); 00418 void DMA_ClearFlag(uint32_t DMAy_FLAG); 00419 ITStatus DMA_GetITStatus(uint32_t DMAy_IT); 00420 void DMA_ClearITPendingBit(uint32_t DMAy_IT); 00421 00422 #ifdef __cplusplus 00423 } 00424 #endif 00425 00426 #endif /*__STM32F10x_DMA_H */ 00427 00439 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
1.7.5 
