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STM32F10x Standard Peripherals Library
3.5.0
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STM32F10x Standard Peripherals Library
3.5.0
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00001 00050 #ifndef __STM32F10x_H 00051 #define __STM32F10x_H 00052 00053 #ifdef __cplusplus 00054 extern "C" { 00055 #endif 00056 00061 /* Uncomment the line below according to the target STM32 device used in your 00062 application 00063 */ 00064 00065 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) 00066 /* #define STM32F10X_LD */ 00067 /* #define STM32F10X_LD_VL */ 00068 /* #define STM32F10X_MD */ 00069 /* #define STM32F10X_MD_VL */ 00070 /* #define STM32F10X_HD */ 00071 /* #define STM32F10X_HD_VL */ 00072 /* #define STM32F10X_XL */ 00073 /* #define STM32F10X_CL */ 00074 #endif 00075 /* Tip: To avoid modifying this file each time you need to switch between these 00076 devices, you can define the device in your toolchain compiler preprocessor. 00077 00078 - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers 00079 where the Flash memory density ranges between 16 and 32 Kbytes. 00080 - Low-density value line devices are STM32F100xx microcontrollers where the Flash 00081 memory density ranges between 16 and 32 Kbytes. 00082 - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers 00083 where the Flash memory density ranges between 64 and 128 Kbytes. 00084 - Medium-density value line devices are STM32F100xx microcontrollers where the 00085 Flash memory density ranges between 64 and 128 Kbytes. 00086 - High-density devices are STM32F101xx and STM32F103xx microcontrollers where 00087 the Flash memory density ranges between 256 and 512 Kbytes. 00088 - High-density value line devices are STM32F100xx microcontrollers where the 00089 Flash memory density ranges between 256 and 512 Kbytes. 00090 - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where 00091 the Flash memory density ranges between 512 and 1024 Kbytes. 00092 - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. 00093 */ 00094 00095 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) 00096 #error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)" 00097 #endif 00098 00099 #if !defined USE_STDPERIPH_DRIVER 00100 00105 /*#define USE_STDPERIPH_DRIVER*/ 00106 #endif 00107 00115 #if !defined HSE_VALUE 00116 #ifdef STM32F10X_CL 00117 #define HSE_VALUE ((uint32_t)25000000) 00118 #else 00119 #define HSE_VALUE ((uint32_t)8000000) 00120 #endif /* STM32F10X_CL */ 00121 #endif /* HSE_VALUE */ 00122 00123 00128 #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) 00130 #define HSI_VALUE ((uint32_t)8000000) 00135 #define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) 00136 #define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x05) 00137 #define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) 00138 #define __STM32F10X_STDPERIPH_VERSION_RC (0x00) 00139 #define __STM32F10X_STDPERIPH_VERSION ( (__STM32F10X_STDPERIPH_VERSION_MAIN << 24)\ 00140 |(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16)\ 00141 |(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8)\ 00142 |(__STM32F10X_STDPERIPH_VERSION_RC)) 00143 00155 #ifdef STM32F10X_XL 00156 #define __MPU_PRESENT 1 00157 #else 00158 #define __MPU_PRESENT 0 00159 #endif /* STM32F10X_XL */ 00160 #define __NVIC_PRIO_BITS 4 00161 #define __Vendor_SysTickConfig 0 00167 typedef enum IRQn 00168 { 00169 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ 00170 NonMaskableInt_IRQn = -14, 00171 MemoryManagement_IRQn = -12, 00172 BusFault_IRQn = -11, 00173 UsageFault_IRQn = -10, 00174 SVCall_IRQn = -5, 00175 DebugMonitor_IRQn = -4, 00176 PendSV_IRQn = -2, 00177 SysTick_IRQn = -1, 00179 /****** STM32 specific Interrupt Numbers *********************************************************/ 00180 WWDG_IRQn = 0, 00181 PVD_IRQn = 1, 00182 TAMPER_IRQn = 2, 00183 RTC_IRQn = 3, 00184 FLASH_IRQn = 4, 00185 RCC_IRQn = 5, 00186 EXTI0_IRQn = 6, 00187 EXTI1_IRQn = 7, 00188 EXTI2_IRQn = 8, 00189 EXTI3_IRQn = 9, 00190 EXTI4_IRQn = 10, 00191 DMA1_Channel1_IRQn = 11, 00192 DMA1_Channel2_IRQn = 12, 00193 DMA1_Channel3_IRQn = 13, 00194 DMA1_Channel4_IRQn = 14, 00195 DMA1_Channel5_IRQn = 15, 00196 DMA1_Channel6_IRQn = 16, 00197 DMA1_Channel7_IRQn = 17, 00199 #ifdef STM32F10X_LD 00200 ADC1_2_IRQn = 18, 00201 USB_HP_CAN1_TX_IRQn = 19, 00202 USB_LP_CAN1_RX0_IRQn = 20, 00203 CAN1_RX1_IRQn = 21, 00204 CAN1_SCE_IRQn = 22, 00205 EXTI9_5_IRQn = 23, 00206 TIM1_BRK_IRQn = 24, 00207 TIM1_UP_IRQn = 25, 00208 TIM1_TRG_COM_IRQn = 26, 00209 TIM1_CC_IRQn = 27, 00210 TIM2_IRQn = 28, 00211 TIM3_IRQn = 29, 00212 I2C1_EV_IRQn = 31, 00213 I2C1_ER_IRQn = 32, 00214 SPI1_IRQn = 35, 00215 USART1_IRQn = 37, 00216 USART2_IRQn = 38, 00217 EXTI15_10_IRQn = 40, 00218 RTCAlarm_IRQn = 41, 00219 USBWakeUp_IRQn = 42 00220 #endif /* STM32F10X_LD */ 00221 00222 #ifdef STM32F10X_LD_VL 00223 ADC1_IRQn = 18, 00224 EXTI9_5_IRQn = 23, 00225 TIM1_BRK_TIM15_IRQn = 24, 00226 TIM1_UP_TIM16_IRQn = 25, 00227 TIM1_TRG_COM_TIM17_IRQn = 26, 00228 TIM1_CC_IRQn = 27, 00229 TIM2_IRQn = 28, 00230 TIM3_IRQn = 29, 00231 I2C1_EV_IRQn = 31, 00232 I2C1_ER_IRQn = 32, 00233 SPI1_IRQn = 35, 00234 USART1_IRQn = 37, 00235 USART2_IRQn = 38, 00236 EXTI15_10_IRQn = 40, 00237 RTCAlarm_IRQn = 41, 00238 CEC_IRQn = 42, 00239 TIM6_DAC_IRQn = 54, 00240 TIM7_IRQn = 55 00241 #endif /* STM32F10X_LD_VL */ 00242 00243 #ifdef STM32F10X_MD 00244 ADC1_2_IRQn = 18, 00245 USB_HP_CAN1_TX_IRQn = 19, 00246 USB_LP_CAN1_RX0_IRQn = 20, 00247 CAN1_RX1_IRQn = 21, 00248 CAN1_SCE_IRQn = 22, 00249 EXTI9_5_IRQn = 23, 00250 TIM1_BRK_IRQn = 24, 00251 TIM1_UP_IRQn = 25, 00252 TIM1_TRG_COM_IRQn = 26, 00253 TIM1_CC_IRQn = 27, 00254 TIM2_IRQn = 28, 00255 TIM3_IRQn = 29, 00256 TIM4_IRQn = 30, 00257 I2C1_EV_IRQn = 31, 00258 I2C1_ER_IRQn = 32, 00259 I2C2_EV_IRQn = 33, 00260 I2C2_ER_IRQn = 34, 00261 SPI1_IRQn = 35, 00262 SPI2_IRQn = 36, 00263 USART1_IRQn = 37, 00264 USART2_IRQn = 38, 00265 USART3_IRQn = 39, 00266 EXTI15_10_IRQn = 40, 00267 RTCAlarm_IRQn = 41, 00268 USBWakeUp_IRQn = 42 00269 #endif /* STM32F10X_MD */ 00270 00271 #ifdef STM32F10X_MD_VL 00272 ADC1_IRQn = 18, 00273 EXTI9_5_IRQn = 23, 00274 TIM1_BRK_TIM15_IRQn = 24, 00275 TIM1_UP_TIM16_IRQn = 25, 00276 TIM1_TRG_COM_TIM17_IRQn = 26, 00277 TIM1_CC_IRQn = 27, 00278 TIM2_IRQn = 28, 00279 TIM3_IRQn = 29, 00280 TIM4_IRQn = 30, 00281 I2C1_EV_IRQn = 31, 00282 I2C1_ER_IRQn = 32, 00283 I2C2_EV_IRQn = 33, 00284 I2C2_ER_IRQn = 34, 00285 SPI1_IRQn = 35, 00286 SPI2_IRQn = 36, 00287 USART1_IRQn = 37, 00288 USART2_IRQn = 38, 00289 USART3_IRQn = 39, 00290 EXTI15_10_IRQn = 40, 00291 RTCAlarm_IRQn = 41, 00292 CEC_IRQn = 42, 00293 TIM6_DAC_IRQn = 54, 00294 TIM7_IRQn = 55 00295 #endif /* STM32F10X_MD_VL */ 00296 00297 #ifdef STM32F10X_HD 00298 ADC1_2_IRQn = 18, 00299 USB_HP_CAN1_TX_IRQn = 19, 00300 USB_LP_CAN1_RX0_IRQn = 20, 00301 CAN1_RX1_IRQn = 21, 00302 CAN1_SCE_IRQn = 22, 00303 EXTI9_5_IRQn = 23, 00304 TIM1_BRK_IRQn = 24, 00305 TIM1_UP_IRQn = 25, 00306 TIM1_TRG_COM_IRQn = 26, 00307 TIM1_CC_IRQn = 27, 00308 TIM2_IRQn = 28, 00309 TIM3_IRQn = 29, 00310 TIM4_IRQn = 30, 00311 I2C1_EV_IRQn = 31, 00312 I2C1_ER_IRQn = 32, 00313 I2C2_EV_IRQn = 33, 00314 I2C2_ER_IRQn = 34, 00315 SPI1_IRQn = 35, 00316 SPI2_IRQn = 36, 00317 USART1_IRQn = 37, 00318 USART2_IRQn = 38, 00319 USART3_IRQn = 39, 00320 EXTI15_10_IRQn = 40, 00321 RTCAlarm_IRQn = 41, 00322 USBWakeUp_IRQn = 42, 00323 TIM8_BRK_IRQn = 43, 00324 TIM8_UP_IRQn = 44, 00325 TIM8_TRG_COM_IRQn = 45, 00326 TIM8_CC_IRQn = 46, 00327 ADC3_IRQn = 47, 00328 FSMC_IRQn = 48, 00329 SDIO_IRQn = 49, 00330 TIM5_IRQn = 50, 00331 SPI3_IRQn = 51, 00332 UART4_IRQn = 52, 00333 UART5_IRQn = 53, 00334 TIM6_IRQn = 54, 00335 TIM7_IRQn = 55, 00336 DMA2_Channel1_IRQn = 56, 00337 DMA2_Channel2_IRQn = 57, 00338 DMA2_Channel3_IRQn = 58, 00339 DMA2_Channel4_5_IRQn = 59 00340 #endif /* STM32F10X_HD */ 00341 00342 #ifdef STM32F10X_HD_VL 00343 ADC1_IRQn = 18, 00344 EXTI9_5_IRQn = 23, 00345 TIM1_BRK_TIM15_IRQn = 24, 00346 TIM1_UP_TIM16_IRQn = 25, 00347 TIM1_TRG_COM_TIM17_IRQn = 26, 00348 TIM1_CC_IRQn = 27, 00349 TIM2_IRQn = 28, 00350 TIM3_IRQn = 29, 00351 TIM4_IRQn = 30, 00352 I2C1_EV_IRQn = 31, 00353 I2C1_ER_IRQn = 32, 00354 I2C2_EV_IRQn = 33, 00355 I2C2_ER_IRQn = 34, 00356 SPI1_IRQn = 35, 00357 SPI2_IRQn = 36, 00358 USART1_IRQn = 37, 00359 USART2_IRQn = 38, 00360 USART3_IRQn = 39, 00361 EXTI15_10_IRQn = 40, 00362 RTCAlarm_IRQn = 41, 00363 CEC_IRQn = 42, 00364 TIM12_IRQn = 43, 00365 TIM13_IRQn = 44, 00366 TIM14_IRQn = 45, 00367 TIM5_IRQn = 50, 00368 SPI3_IRQn = 51, 00369 UART4_IRQn = 52, 00370 UART5_IRQn = 53, 00371 TIM6_DAC_IRQn = 54, 00372 TIM7_IRQn = 55, 00373 DMA2_Channel1_IRQn = 56, 00374 DMA2_Channel2_IRQn = 57, 00375 DMA2_Channel3_IRQn = 58, 00376 DMA2_Channel4_5_IRQn = 59, 00377 DMA2_Channel5_IRQn = 60 00380 #endif /* STM32F10X_HD_VL */ 00381 00382 #ifdef STM32F10X_XL 00383 ADC1_2_IRQn = 18, 00384 USB_HP_CAN1_TX_IRQn = 19, 00385 USB_LP_CAN1_RX0_IRQn = 20, 00386 CAN1_RX1_IRQn = 21, 00387 CAN1_SCE_IRQn = 22, 00388 EXTI9_5_IRQn = 23, 00389 TIM1_BRK_TIM9_IRQn = 24, 00390 TIM1_UP_TIM10_IRQn = 25, 00391 TIM1_TRG_COM_TIM11_IRQn = 26, 00392 TIM1_CC_IRQn = 27, 00393 TIM2_IRQn = 28, 00394 TIM3_IRQn = 29, 00395 TIM4_IRQn = 30, 00396 I2C1_EV_IRQn = 31, 00397 I2C1_ER_IRQn = 32, 00398 I2C2_EV_IRQn = 33, 00399 I2C2_ER_IRQn = 34, 00400 SPI1_IRQn = 35, 00401 SPI2_IRQn = 36, 00402 USART1_IRQn = 37, 00403 USART2_IRQn = 38, 00404 USART3_IRQn = 39, 00405 EXTI15_10_IRQn = 40, 00406 RTCAlarm_IRQn = 41, 00407 USBWakeUp_IRQn = 42, 00408 TIM8_BRK_TIM12_IRQn = 43, 00409 TIM8_UP_TIM13_IRQn = 44, 00410 TIM8_TRG_COM_TIM14_IRQn = 45, 00411 TIM8_CC_IRQn = 46, 00412 ADC3_IRQn = 47, 00413 FSMC_IRQn = 48, 00414 SDIO_IRQn = 49, 00415 TIM5_IRQn = 50, 00416 SPI3_IRQn = 51, 00417 UART4_IRQn = 52, 00418 UART5_IRQn = 53, 00419 TIM6_IRQn = 54, 00420 TIM7_IRQn = 55, 00421 DMA2_Channel1_IRQn = 56, 00422 DMA2_Channel2_IRQn = 57, 00423 DMA2_Channel3_IRQn = 58, 00424 DMA2_Channel4_5_IRQn = 59 00425 #endif /* STM32F10X_XL */ 00426 00427 #ifdef STM32F10X_CL 00428 ADC1_2_IRQn = 18, 00429 CAN1_TX_IRQn = 19, 00430 CAN1_RX0_IRQn = 20, 00431 CAN1_RX1_IRQn = 21, 00432 CAN1_SCE_IRQn = 22, 00433 EXTI9_5_IRQn = 23, 00434 TIM1_BRK_IRQn = 24, 00435 TIM1_UP_IRQn = 25, 00436 TIM1_TRG_COM_IRQn = 26, 00437 TIM1_CC_IRQn = 27, 00438 TIM2_IRQn = 28, 00439 TIM3_IRQn = 29, 00440 TIM4_IRQn = 30, 00441 I2C1_EV_IRQn = 31, 00442 I2C1_ER_IRQn = 32, 00443 I2C2_EV_IRQn = 33, 00444 I2C2_ER_IRQn = 34, 00445 SPI1_IRQn = 35, 00446 SPI2_IRQn = 36, 00447 USART1_IRQn = 37, 00448 USART2_IRQn = 38, 00449 USART3_IRQn = 39, 00450 EXTI15_10_IRQn = 40, 00451 RTCAlarm_IRQn = 41, 00452 OTG_FS_WKUP_IRQn = 42, 00453 TIM5_IRQn = 50, 00454 SPI3_IRQn = 51, 00455 UART4_IRQn = 52, 00456 UART5_IRQn = 53, 00457 TIM6_IRQn = 54, 00458 TIM7_IRQn = 55, 00459 DMA2_Channel1_IRQn = 56, 00460 DMA2_Channel2_IRQn = 57, 00461 DMA2_Channel3_IRQn = 58, 00462 DMA2_Channel4_IRQn = 59, 00463 DMA2_Channel5_IRQn = 60, 00464 ETH_IRQn = 61, 00465 ETH_WKUP_IRQn = 62, 00466 CAN2_TX_IRQn = 63, 00467 CAN2_RX0_IRQn = 64, 00468 CAN2_RX1_IRQn = 65, 00469 CAN2_SCE_IRQn = 66, 00470 OTG_FS_IRQn = 67 00471 #endif /* STM32F10X_CL */ 00472 } IRQn_Type; 00473 00478 #include "core_cm3.h" 00479 #include "system_stm32f10x.h" 00480 #include <stdint.h> 00481 00487 typedef int32_t s32; 00488 typedef int16_t s16; 00489 typedef int8_t s8; 00490 00491 typedef const int32_t sc32; 00492 typedef const int16_t sc16; 00493 typedef const int8_t sc8; 00495 typedef __IO int32_t vs32; 00496 typedef __IO int16_t vs16; 00497 typedef __IO int8_t vs8; 00498 00499 typedef __I int32_t vsc32; 00500 typedef __I int16_t vsc16; 00501 typedef __I int8_t vsc8; 00503 typedef uint32_t u32; 00504 typedef uint16_t u16; 00505 typedef uint8_t u8; 00506 00507 typedef const uint32_t uc32; 00508 typedef const uint16_t uc16; 00509 typedef const uint8_t uc8; 00511 typedef __IO uint32_t vu32; 00512 typedef __IO uint16_t vu16; 00513 typedef __IO uint8_t vu8; 00514 00515 typedef __I uint32_t vuc32; 00516 typedef __I uint16_t vuc16; 00517 typedef __I uint8_t vuc8; 00519 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; 00520 00521 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; 00522 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) 00523 00524 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; 00525 00527 #define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT 00528 #define HSE_Value HSE_VALUE 00529 #define HSI_Value HSI_VALUE 00530 00542 typedef struct 00543 { 00544 __IO uint32_t SR; 00545 __IO uint32_t CR1; 00546 __IO uint32_t CR2; 00547 __IO uint32_t SMPR1; 00548 __IO uint32_t SMPR2; 00549 __IO uint32_t JOFR1; 00550 __IO uint32_t JOFR2; 00551 __IO uint32_t JOFR3; 00552 __IO uint32_t JOFR4; 00553 __IO uint32_t HTR; 00554 __IO uint32_t LTR; 00555 __IO uint32_t SQR1; 00556 __IO uint32_t SQR2; 00557 __IO uint32_t SQR3; 00558 __IO uint32_t JSQR; 00559 __IO uint32_t JDR1; 00560 __IO uint32_t JDR2; 00561 __IO uint32_t JDR3; 00562 __IO uint32_t JDR4; 00563 __IO uint32_t DR; 00564 } ADC_TypeDef; 00565 00570 typedef struct 00571 { 00572 uint32_t RESERVED0; 00573 __IO uint16_t DR1; 00574 uint16_t RESERVED1; 00575 __IO uint16_t DR2; 00576 uint16_t RESERVED2; 00577 __IO uint16_t DR3; 00578 uint16_t RESERVED3; 00579 __IO uint16_t DR4; 00580 uint16_t RESERVED4; 00581 __IO uint16_t DR5; 00582 uint16_t RESERVED5; 00583 __IO uint16_t DR6; 00584 uint16_t RESERVED6; 00585 __IO uint16_t DR7; 00586 uint16_t RESERVED7; 00587 __IO uint16_t DR8; 00588 uint16_t RESERVED8; 00589 __IO uint16_t DR9; 00590 uint16_t RESERVED9; 00591 __IO uint16_t DR10; 00592 uint16_t RESERVED10; 00593 __IO uint16_t RTCCR; 00594 uint16_t RESERVED11; 00595 __IO uint16_t CR; 00596 uint16_t RESERVED12; 00597 __IO uint16_t CSR; 00598 uint16_t RESERVED13[5]; 00599 __IO uint16_t DR11; 00600 uint16_t RESERVED14; 00601 __IO uint16_t DR12; 00602 uint16_t RESERVED15; 00603 __IO uint16_t DR13; 00604 uint16_t RESERVED16; 00605 __IO uint16_t DR14; 00606 uint16_t RESERVED17; 00607 __IO uint16_t DR15; 00608 uint16_t RESERVED18; 00609 __IO uint16_t DR16; 00610 uint16_t RESERVED19; 00611 __IO uint16_t DR17; 00612 uint16_t RESERVED20; 00613 __IO uint16_t DR18; 00614 uint16_t RESERVED21; 00615 __IO uint16_t DR19; 00616 uint16_t RESERVED22; 00617 __IO uint16_t DR20; 00618 uint16_t RESERVED23; 00619 __IO uint16_t DR21; 00620 uint16_t RESERVED24; 00621 __IO uint16_t DR22; 00622 uint16_t RESERVED25; 00623 __IO uint16_t DR23; 00624 uint16_t RESERVED26; 00625 __IO uint16_t DR24; 00626 uint16_t RESERVED27; 00627 __IO uint16_t DR25; 00628 uint16_t RESERVED28; 00629 __IO uint16_t DR26; 00630 uint16_t RESERVED29; 00631 __IO uint16_t DR27; 00632 uint16_t RESERVED30; 00633 __IO uint16_t DR28; 00634 uint16_t RESERVED31; 00635 __IO uint16_t DR29; 00636 uint16_t RESERVED32; 00637 __IO uint16_t DR30; 00638 uint16_t RESERVED33; 00639 __IO uint16_t DR31; 00640 uint16_t RESERVED34; 00641 __IO uint16_t DR32; 00642 uint16_t RESERVED35; 00643 __IO uint16_t DR33; 00644 uint16_t RESERVED36; 00645 __IO uint16_t DR34; 00646 uint16_t RESERVED37; 00647 __IO uint16_t DR35; 00648 uint16_t RESERVED38; 00649 __IO uint16_t DR36; 00650 uint16_t RESERVED39; 00651 __IO uint16_t DR37; 00652 uint16_t RESERVED40; 00653 __IO uint16_t DR38; 00654 uint16_t RESERVED41; 00655 __IO uint16_t DR39; 00656 uint16_t RESERVED42; 00657 __IO uint16_t DR40; 00658 uint16_t RESERVED43; 00659 __IO uint16_t DR41; 00660 uint16_t RESERVED44; 00661 __IO uint16_t DR42; 00662 uint16_t RESERVED45; 00663 } BKP_TypeDef; 00664 00669 typedef struct 00670 { 00671 __IO uint32_t TIR; 00672 __IO uint32_t TDTR; 00673 __IO uint32_t TDLR; 00674 __IO uint32_t TDHR; 00675 } CAN_TxMailBox_TypeDef; 00676 00681 typedef struct 00682 { 00683 __IO uint32_t RIR; 00684 __IO uint32_t RDTR; 00685 __IO uint32_t RDLR; 00686 __IO uint32_t RDHR; 00687 } CAN_FIFOMailBox_TypeDef; 00688 00693 typedef struct 00694 { 00695 __IO uint32_t FR1; 00696 __IO uint32_t FR2; 00697 } CAN_FilterRegister_TypeDef; 00698 00703 typedef struct 00704 { 00705 __IO uint32_t MCR; 00706 __IO uint32_t MSR; 00707 __IO uint32_t TSR; 00708 __IO uint32_t RF0R; 00709 __IO uint32_t RF1R; 00710 __IO uint32_t IER; 00711 __IO uint32_t ESR; 00712 __IO uint32_t BTR; 00713 uint32_t RESERVED0[88]; 00714 CAN_TxMailBox_TypeDef sTxMailBox[3]; 00715 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; 00716 uint32_t RESERVED1[12]; 00717 __IO uint32_t FMR; 00718 __IO uint32_t FM1R; 00719 uint32_t RESERVED2; 00720 __IO uint32_t FS1R; 00721 uint32_t RESERVED3; 00722 __IO uint32_t FFA1R; 00723 uint32_t RESERVED4; 00724 __IO uint32_t FA1R; 00725 uint32_t RESERVED5[8]; 00726 #ifndef STM32F10X_CL 00727 CAN_FilterRegister_TypeDef sFilterRegister[14]; 00728 #else 00729 CAN_FilterRegister_TypeDef sFilterRegister[28]; 00730 #endif /* STM32F10X_CL */ 00731 } CAN_TypeDef; 00732 00736 typedef struct 00737 { 00738 __IO uint32_t CFGR; 00739 __IO uint32_t OAR; 00740 __IO uint32_t PRES; 00741 __IO uint32_t ESR; 00742 __IO uint32_t CSR; 00743 __IO uint32_t TXD; 00744 __IO uint32_t RXD; 00745 } CEC_TypeDef; 00746 00751 typedef struct 00752 { 00753 __IO uint32_t DR; 00754 __IO uint8_t IDR; 00755 uint8_t RESERVED0; 00756 uint16_t RESERVED1; 00757 __IO uint32_t CR; 00758 } CRC_TypeDef; 00759 00764 typedef struct 00765 { 00766 __IO uint32_t CR; 00767 __IO uint32_t SWTRIGR; 00768 __IO uint32_t DHR12R1; 00769 __IO uint32_t DHR12L1; 00770 __IO uint32_t DHR8R1; 00771 __IO uint32_t DHR12R2; 00772 __IO uint32_t DHR12L2; 00773 __IO uint32_t DHR8R2; 00774 __IO uint32_t DHR12RD; 00775 __IO uint32_t DHR12LD; 00776 __IO uint32_t DHR8RD; 00777 __IO uint32_t DOR1; 00778 __IO uint32_t DOR2; 00779 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) 00780 __IO uint32_t SR; 00781 #endif 00782 } DAC_TypeDef; 00783 00788 typedef struct 00789 { 00790 __IO uint32_t IDCODE; 00791 __IO uint32_t CR; 00792 }DBGMCU_TypeDef; 00793 00798 typedef struct 00799 { 00800 __IO uint32_t CCR; 00801 __IO uint32_t CNDTR; 00802 __IO uint32_t CPAR; 00803 __IO uint32_t CMAR; 00804 } DMA_Channel_TypeDef; 00805 00806 typedef struct 00807 { 00808 __IO uint32_t ISR; 00809 __IO uint32_t IFCR; 00810 } DMA_TypeDef; 00811 00816 typedef struct 00817 { 00818 __IO uint32_t MACCR; 00819 __IO uint32_t MACFFR; 00820 __IO uint32_t MACHTHR; 00821 __IO uint32_t MACHTLR; 00822 __IO uint32_t MACMIIAR; 00823 __IO uint32_t MACMIIDR; 00824 __IO uint32_t MACFCR; 00825 __IO uint32_t MACVLANTR; /* 8 */ 00826 uint32_t RESERVED0[2]; 00827 __IO uint32_t MACRWUFFR; /* 11 */ 00828 __IO uint32_t MACPMTCSR; 00829 uint32_t RESERVED1[2]; 00830 __IO uint32_t MACSR; /* 15 */ 00831 __IO uint32_t MACIMR; 00832 __IO uint32_t MACA0HR; 00833 __IO uint32_t MACA0LR; 00834 __IO uint32_t MACA1HR; 00835 __IO uint32_t MACA1LR; 00836 __IO uint32_t MACA2HR; 00837 __IO uint32_t MACA2LR; 00838 __IO uint32_t MACA3HR; 00839 __IO uint32_t MACA3LR; /* 24 */ 00840 uint32_t RESERVED2[40]; 00841 __IO uint32_t MMCCR; /* 65 */ 00842 __IO uint32_t MMCRIR; 00843 __IO uint32_t MMCTIR; 00844 __IO uint32_t MMCRIMR; 00845 __IO uint32_t MMCTIMR; /* 69 */ 00846 uint32_t RESERVED3[14]; 00847 __IO uint32_t MMCTGFSCCR; /* 84 */ 00848 __IO uint32_t MMCTGFMSCCR; 00849 uint32_t RESERVED4[5]; 00850 __IO uint32_t MMCTGFCR; 00851 uint32_t RESERVED5[10]; 00852 __IO uint32_t MMCRFCECR; 00853 __IO uint32_t MMCRFAECR; 00854 uint32_t RESERVED6[10]; 00855 __IO uint32_t MMCRGUFCR; 00856 uint32_t RESERVED7[334]; 00857 __IO uint32_t PTPTSCR; 00858 __IO uint32_t PTPSSIR; 00859 __IO uint32_t PTPTSHR; 00860 __IO uint32_t PTPTSLR; 00861 __IO uint32_t PTPTSHUR; 00862 __IO uint32_t PTPTSLUR; 00863 __IO uint32_t PTPTSAR; 00864 __IO uint32_t PTPTTHR; 00865 __IO uint32_t PTPTTLR; 00866 uint32_t RESERVED8[567]; 00867 __IO uint32_t DMABMR; 00868 __IO uint32_t DMATPDR; 00869 __IO uint32_t DMARPDR; 00870 __IO uint32_t DMARDLAR; 00871 __IO uint32_t DMATDLAR; 00872 __IO uint32_t DMASR; 00873 __IO uint32_t DMAOMR; 00874 __IO uint32_t DMAIER; 00875 __IO uint32_t DMAMFBOCR; 00876 uint32_t RESERVED9[9]; 00877 __IO uint32_t DMACHTDR; 00878 __IO uint32_t DMACHRDR; 00879 __IO uint32_t DMACHTBAR; 00880 __IO uint32_t DMACHRBAR; 00881 } ETH_TypeDef; 00882 00887 typedef struct 00888 { 00889 __IO uint32_t IMR; 00890 __IO uint32_t EMR; 00891 __IO uint32_t RTSR; 00892 __IO uint32_t FTSR; 00893 __IO uint32_t SWIER; 00894 __IO uint32_t PR; 00895 } EXTI_TypeDef; 00896 00901 typedef struct 00902 { 00903 __IO uint32_t ACR; 00904 __IO uint32_t KEYR; 00905 __IO uint32_t OPTKEYR; 00906 __IO uint32_t SR; 00907 __IO uint32_t CR; 00908 __IO uint32_t AR; 00909 __IO uint32_t RESERVED; 00910 __IO uint32_t OBR; 00911 __IO uint32_t WRPR; 00912 #ifdef STM32F10X_XL 00913 uint32_t RESERVED1[8]; 00914 __IO uint32_t KEYR2; 00915 uint32_t RESERVED2; 00916 __IO uint32_t SR2; 00917 __IO uint32_t CR2; 00918 __IO uint32_t AR2; 00919 #endif /* STM32F10X_XL */ 00920 } FLASH_TypeDef; 00921 00926 typedef struct 00927 { 00928 __IO uint16_t RDP; 00929 __IO uint16_t USER; 00930 __IO uint16_t Data0; 00931 __IO uint16_t Data1; 00932 __IO uint16_t WRP0; 00933 __IO uint16_t WRP1; 00934 __IO uint16_t WRP2; 00935 __IO uint16_t WRP3; 00936 } OB_TypeDef; 00937 00942 typedef struct 00943 { 00944 __IO uint32_t BTCR[8]; 00945 } FSMC_Bank1_TypeDef; 00946 00951 typedef struct 00952 { 00953 __IO uint32_t BWTR[7]; 00954 } FSMC_Bank1E_TypeDef; 00955 00960 typedef struct 00961 { 00962 __IO uint32_t PCR2; 00963 __IO uint32_t SR2; 00964 __IO uint32_t PMEM2; 00965 __IO uint32_t PATT2; 00966 uint32_t RESERVED0; 00967 __IO uint32_t ECCR2; 00968 } FSMC_Bank2_TypeDef; 00969 00974 typedef struct 00975 { 00976 __IO uint32_t PCR3; 00977 __IO uint32_t SR3; 00978 __IO uint32_t PMEM3; 00979 __IO uint32_t PATT3; 00980 uint32_t RESERVED0; 00981 __IO uint32_t ECCR3; 00982 } FSMC_Bank3_TypeDef; 00983 00988 typedef struct 00989 { 00990 __IO uint32_t PCR4; 00991 __IO uint32_t SR4; 00992 __IO uint32_t PMEM4; 00993 __IO uint32_t PATT4; 00994 __IO uint32_t PIO4; 00995 } FSMC_Bank4_TypeDef; 00996 01001 typedef struct 01002 { 01003 __IO uint32_t CRL; 01004 __IO uint32_t CRH; 01005 __IO uint32_t IDR; 01006 __IO uint32_t ODR; 01007 __IO uint32_t BSRR; 01008 __IO uint32_t BRR; 01009 __IO uint32_t LCKR; 01010 } GPIO_TypeDef; 01011 01016 typedef struct 01017 { 01018 __IO uint32_t EVCR; 01019 __IO uint32_t MAPR; 01020 __IO uint32_t EXTICR[4]; 01021 uint32_t RESERVED0; 01022 __IO uint32_t MAPR2; 01023 } AFIO_TypeDef; 01028 typedef struct 01029 { 01030 __IO uint16_t CR1; 01031 uint16_t RESERVED0; 01032 __IO uint16_t CR2; 01033 uint16_t RESERVED1; 01034 __IO uint16_t OAR1; 01035 uint16_t RESERVED2; 01036 __IO uint16_t OAR2; 01037 uint16_t RESERVED3; 01038 __IO uint16_t DR; 01039 uint16_t RESERVED4; 01040 __IO uint16_t SR1; 01041 uint16_t RESERVED5; 01042 __IO uint16_t SR2; 01043 uint16_t RESERVED6; 01044 __IO uint16_t CCR; 01045 uint16_t RESERVED7; 01046 __IO uint16_t TRISE; 01047 uint16_t RESERVED8; 01048 } I2C_TypeDef; 01049 01054 typedef struct 01055 { 01056 __IO uint32_t KR; 01057 __IO uint32_t PR; 01058 __IO uint32_t RLR; 01059 __IO uint32_t SR; 01060 } IWDG_TypeDef; 01061 01066 typedef struct 01067 { 01068 __IO uint32_t CR; 01069 __IO uint32_t CSR; 01070 } PWR_TypeDef; 01071 01076 typedef struct 01077 { 01078 __IO uint32_t CR; 01079 __IO uint32_t CFGR; 01080 __IO uint32_t CIR; 01081 __IO uint32_t APB2RSTR; 01082 __IO uint32_t APB1RSTR; 01083 __IO uint32_t AHBENR; 01084 __IO uint32_t APB2ENR; 01085 __IO uint32_t APB1ENR; 01086 __IO uint32_t BDCR; 01087 __IO uint32_t CSR; 01088 01089 #ifdef STM32F10X_CL 01090 __IO uint32_t AHBRSTR; 01091 __IO uint32_t CFGR2; 01092 #endif /* STM32F10X_CL */ 01093 01094 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) 01095 uint32_t RESERVED0; 01096 __IO uint32_t CFGR2; 01097 #endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */ 01098 } RCC_TypeDef; 01099 01104 typedef struct 01105 { 01106 __IO uint16_t CRH; 01107 uint16_t RESERVED0; 01108 __IO uint16_t CRL; 01109 uint16_t RESERVED1; 01110 __IO uint16_t PRLH; 01111 uint16_t RESERVED2; 01112 __IO uint16_t PRLL; 01113 uint16_t RESERVED3; 01114 __IO uint16_t DIVH; 01115 uint16_t RESERVED4; 01116 __IO uint16_t DIVL; 01117 uint16_t RESERVED5; 01118 __IO uint16_t CNTH; 01119 uint16_t RESERVED6; 01120 __IO uint16_t CNTL; 01121 uint16_t RESERVED7; 01122 __IO uint16_t ALRH; 01123 uint16_t RESERVED8; 01124 __IO uint16_t ALRL; 01125 uint16_t RESERVED9; 01126 } RTC_TypeDef; 01127 01132 typedef struct 01133 { 01134 __IO uint32_t POWER; 01135 __IO uint32_t CLKCR; 01136 __IO uint32_t ARG; 01137 __IO uint32_t CMD; 01138 __I uint32_t RESPCMD; 01139 __I uint32_t RESP1; 01140 __I uint32_t RESP2; 01141 __I uint32_t RESP3; 01142 __I uint32_t RESP4; 01143 __IO uint32_t DTIMER; 01144 __IO uint32_t DLEN; 01145 __IO uint32_t DCTRL; 01146 __I uint32_t DCOUNT; 01147 __I uint32_t STA; 01148 __IO uint32_t ICR; 01149 __IO uint32_t MASK; 01150 uint32_t RESERVED0[2]; 01151 __I uint32_t FIFOCNT; 01152 uint32_t RESERVED1[13]; 01153 __IO uint32_t FIFO; 01154 } SDIO_TypeDef; 01155 01160 typedef struct 01161 { 01162 __IO uint16_t CR1; 01163 uint16_t RESERVED0; 01164 __IO uint16_t CR2; 01165 uint16_t RESERVED1; 01166 __IO uint16_t SR; 01167 uint16_t RESERVED2; 01168 __IO uint16_t DR; 01169 uint16_t RESERVED3; 01170 __IO uint16_t CRCPR; 01171 uint16_t RESERVED4; 01172 __IO uint16_t RXCRCR; 01173 uint16_t RESERVED5; 01174 __IO uint16_t TXCRCR; 01175 uint16_t RESERVED6; 01176 __IO uint16_t I2SCFGR; 01177 uint16_t RESERVED7; 01178 __IO uint16_t I2SPR; 01179 uint16_t RESERVED8; 01180 } SPI_TypeDef; 01181 01186 typedef struct 01187 { 01188 __IO uint16_t CR1; 01189 uint16_t RESERVED0; 01190 __IO uint16_t CR2; 01191 uint16_t RESERVED1; 01192 __IO uint16_t SMCR; 01193 uint16_t RESERVED2; 01194 __IO uint16_t DIER; 01195 uint16_t RESERVED3; 01196 __IO uint16_t SR; 01197 uint16_t RESERVED4; 01198 __IO uint16_t EGR; 01199 uint16_t RESERVED5; 01200 __IO uint16_t CCMR1; 01201 uint16_t RESERVED6; 01202 __IO uint16_t CCMR2; 01203 uint16_t RESERVED7; 01204 __IO uint16_t CCER; 01205 uint16_t RESERVED8; 01206 __IO uint16_t CNT; 01207 uint16_t RESERVED9; 01208 __IO uint16_t PSC; 01209 uint16_t RESERVED10; 01210 __IO uint16_t ARR; 01211 uint16_t RESERVED11; 01212 __IO uint16_t RCR; 01213 uint16_t RESERVED12; 01214 __IO uint16_t CCR1; 01215 uint16_t RESERVED13; 01216 __IO uint16_t CCR2; 01217 uint16_t RESERVED14; 01218 __IO uint16_t CCR3; 01219 uint16_t RESERVED15; 01220 __IO uint16_t CCR4; 01221 uint16_t RESERVED16; 01222 __IO uint16_t BDTR; 01223 uint16_t RESERVED17; 01224 __IO uint16_t DCR; 01225 uint16_t RESERVED18; 01226 __IO uint16_t DMAR; 01227 uint16_t RESERVED19; 01228 } TIM_TypeDef; 01229 01234 typedef struct 01235 { 01236 __IO uint16_t SR; 01237 uint16_t RESERVED0; 01238 __IO uint16_t DR; 01239 uint16_t RESERVED1; 01240 __IO uint16_t BRR; 01241 uint16_t RESERVED2; 01242 __IO uint16_t CR1; 01243 uint16_t RESERVED3; 01244 __IO uint16_t CR2; 01245 uint16_t RESERVED4; 01246 __IO uint16_t CR3; 01247 uint16_t RESERVED5; 01248 __IO uint16_t GTPR; 01249 uint16_t RESERVED6; 01250 } USART_TypeDef; 01251 01256 typedef struct 01257 { 01258 __IO uint32_t CR; 01259 __IO uint32_t CFR; 01260 __IO uint32_t SR; 01261 } WWDG_TypeDef; 01262 01272 #define FLASH_BASE ((uint32_t)0x08000000) 01273 #define SRAM_BASE ((uint32_t)0x20000000) 01274 #define PERIPH_BASE ((uint32_t)0x40000000) 01276 #define SRAM_BB_BASE ((uint32_t)0x22000000) 01277 #define PERIPH_BB_BASE ((uint32_t)0x42000000) 01279 #define FSMC_R_BASE ((uint32_t)0xA0000000) 01282 #define APB1PERIPH_BASE PERIPH_BASE 01283 #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) 01284 #define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) 01285 01286 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000) 01287 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400) 01288 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) 01289 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) 01290 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000) 01291 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400) 01292 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800) 01293 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) 01294 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000) 01295 #define RTC_BASE (APB1PERIPH_BASE + 0x2800) 01296 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) 01297 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000) 01298 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800) 01299 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) 01300 #define USART2_BASE (APB1PERIPH_BASE + 0x4400) 01301 #define USART3_BASE (APB1PERIPH_BASE + 0x4800) 01302 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00) 01303 #define UART5_BASE (APB1PERIPH_BASE + 0x5000) 01304 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400) 01305 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800) 01306 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400) 01307 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800) 01308 #define BKP_BASE (APB1PERIPH_BASE + 0x6C00) 01309 #define PWR_BASE (APB1PERIPH_BASE + 0x7000) 01310 #define DAC_BASE (APB1PERIPH_BASE + 0x7400) 01311 #define CEC_BASE (APB1PERIPH_BASE + 0x7800) 01312 01313 #define AFIO_BASE (APB2PERIPH_BASE + 0x0000) 01314 #define EXTI_BASE (APB2PERIPH_BASE + 0x0400) 01315 #define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) 01316 #define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) 01317 #define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) 01318 #define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) 01319 #define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) 01320 #define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) 01321 #define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) 01322 #define ADC1_BASE (APB2PERIPH_BASE + 0x2400) 01323 #define ADC2_BASE (APB2PERIPH_BASE + 0x2800) 01324 #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) 01325 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000) 01326 #define TIM8_BASE (APB2PERIPH_BASE + 0x3400) 01327 #define USART1_BASE (APB2PERIPH_BASE + 0x3800) 01328 #define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) 01329 #define TIM15_BASE (APB2PERIPH_BASE + 0x4000) 01330 #define TIM16_BASE (APB2PERIPH_BASE + 0x4400) 01331 #define TIM17_BASE (APB2PERIPH_BASE + 0x4800) 01332 #define TIM9_BASE (APB2PERIPH_BASE + 0x4C00) 01333 #define TIM10_BASE (APB2PERIPH_BASE + 0x5000) 01334 #define TIM11_BASE (APB2PERIPH_BASE + 0x5400) 01335 01336 #define SDIO_BASE (PERIPH_BASE + 0x18000) 01337 01338 #define DMA1_BASE (AHBPERIPH_BASE + 0x0000) 01339 #define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) 01340 #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) 01341 #define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) 01342 #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) 01343 #define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) 01344 #define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) 01345 #define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) 01346 #define DMA2_BASE (AHBPERIPH_BASE + 0x0400) 01347 #define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) 01348 #define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) 01349 #define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) 01350 #define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) 01351 #define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) 01352 #define RCC_BASE (AHBPERIPH_BASE + 0x1000) 01353 #define CRC_BASE (AHBPERIPH_BASE + 0x3000) 01354 01355 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) 01356 #define OB_BASE ((uint32_t)0x1FFFF800) 01358 #define ETH_BASE (AHBPERIPH_BASE + 0x8000) 01359 #define ETH_MAC_BASE (ETH_BASE) 01360 #define ETH_MMC_BASE (ETH_BASE + 0x0100) 01361 #define ETH_PTP_BASE (ETH_BASE + 0x0700) 01362 #define ETH_DMA_BASE (ETH_BASE + 0x1000) 01363 01364 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) 01365 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) 01366 #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) 01367 #define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) 01368 #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) 01370 #define DBGMCU_BASE ((uint32_t)0xE0042000) 01380 #define TIM2 ((TIM_TypeDef *) TIM2_BASE) 01381 #define TIM3 ((TIM_TypeDef *) TIM3_BASE) 01382 #define TIM4 ((TIM_TypeDef *) TIM4_BASE) 01383 #define TIM5 ((TIM_TypeDef *) TIM5_BASE) 01384 #define TIM6 ((TIM_TypeDef *) TIM6_BASE) 01385 #define TIM7 ((TIM_TypeDef *) TIM7_BASE) 01386 #define TIM12 ((TIM_TypeDef *) TIM12_BASE) 01387 #define TIM13 ((TIM_TypeDef *) TIM13_BASE) 01388 #define TIM14 ((TIM_TypeDef *) TIM14_BASE) 01389 #define RTC ((RTC_TypeDef *) RTC_BASE) 01390 #define WWDG ((WWDG_TypeDef *) WWDG_BASE) 01391 #define IWDG ((IWDG_TypeDef *) IWDG_BASE) 01392 #define SPI2 ((SPI_TypeDef *) SPI2_BASE) 01393 #define SPI3 ((SPI_TypeDef *) SPI3_BASE) 01394 #define USART2 ((USART_TypeDef *) USART2_BASE) 01395 #define USART3 ((USART_TypeDef *) USART3_BASE) 01396 #define UART4 ((USART_TypeDef *) UART4_BASE) 01397 #define UART5 ((USART_TypeDef *) UART5_BASE) 01398 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) 01399 #define I2C2 ((I2C_TypeDef *) I2C2_BASE) 01400 #define CAN1 ((CAN_TypeDef *) CAN1_BASE) 01401 #define CAN2 ((CAN_TypeDef *) CAN2_BASE) 01402 #define BKP ((BKP_TypeDef *) BKP_BASE) 01403 #define PWR ((PWR_TypeDef *) PWR_BASE) 01404 #define DAC ((DAC_TypeDef *) DAC_BASE) 01405 #define CEC ((CEC_TypeDef *) CEC_BASE) 01406 #define AFIO ((AFIO_TypeDef *) AFIO_BASE) 01407 #define EXTI ((EXTI_TypeDef *) EXTI_BASE) 01408 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) 01409 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) 01410 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) 01411 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) 01412 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) 01413 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) 01414 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) 01415 #define ADC1 ((ADC_TypeDef *) ADC1_BASE) 01416 #define ADC2 ((ADC_TypeDef *) ADC2_BASE) 01417 #define TIM1 ((TIM_TypeDef *) TIM1_BASE) 01418 #define SPI1 ((SPI_TypeDef *) SPI1_BASE) 01419 #define TIM8 ((TIM_TypeDef *) TIM8_BASE) 01420 #define USART1 ((USART_TypeDef *) USART1_BASE) 01421 #define ADC3 ((ADC_TypeDef *) ADC3_BASE) 01422 #define TIM15 ((TIM_TypeDef *) TIM15_BASE) 01423 #define TIM16 ((TIM_TypeDef *) TIM16_BASE) 01424 #define TIM17 ((TIM_TypeDef *) TIM17_BASE) 01425 #define TIM9 ((TIM_TypeDef *) TIM9_BASE) 01426 #define TIM10 ((TIM_TypeDef *) TIM10_BASE) 01427 #define TIM11 ((TIM_TypeDef *) TIM11_BASE) 01428 #define SDIO ((SDIO_TypeDef *) SDIO_BASE) 01429 #define DMA1 ((DMA_TypeDef *) DMA1_BASE) 01430 #define DMA2 ((DMA_TypeDef *) DMA2_BASE) 01431 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) 01432 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) 01433 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) 01434 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) 01435 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) 01436 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) 01437 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) 01438 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) 01439 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) 01440 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) 01441 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) 01442 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) 01443 #define RCC ((RCC_TypeDef *) RCC_BASE) 01444 #define CRC ((CRC_TypeDef *) CRC_BASE) 01445 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) 01446 #define OB ((OB_TypeDef *) OB_BASE) 01447 #define ETH ((ETH_TypeDef *) ETH_BASE) 01448 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) 01449 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) 01450 #define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) 01451 #define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) 01452 #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) 01453 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) 01454 01467 /******************************************************************************/ 01468 /* Peripheral Registers_Bits_Definition */ 01469 /******************************************************************************/ 01470 01471 /******************************************************************************/ 01472 /* */ 01473 /* CRC calculation unit */ 01474 /* */ 01475 /******************************************************************************/ 01476 01477 /******************* Bit definition for CRC_DR register *********************/ 01478 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) 01481 /******************* Bit definition for CRC_IDR register ********************/ 01482 #define CRC_IDR_IDR ((uint8_t)0xFF) 01485 /******************** Bit definition for CRC_CR register ********************/ 01486 #define CRC_CR_RESET ((uint8_t)0x01) 01488 /******************************************************************************/ 01489 /* */ 01490 /* Power Control */ 01491 /* */ 01492 /******************************************************************************/ 01493 01494 /******************** Bit definition for PWR_CR register ********************/ 01495 #define PWR_CR_LPDS ((uint16_t)0x0001) 01496 #define PWR_CR_PDDS ((uint16_t)0x0002) 01497 #define PWR_CR_CWUF ((uint16_t)0x0004) 01498 #define PWR_CR_CSBF ((uint16_t)0x0008) 01499 #define PWR_CR_PVDE ((uint16_t)0x0010) 01501 #define PWR_CR_PLS ((uint16_t)0x00E0) 01502 #define PWR_CR_PLS_0 ((uint16_t)0x0020) 01503 #define PWR_CR_PLS_1 ((uint16_t)0x0040) 01504 #define PWR_CR_PLS_2 ((uint16_t)0x0080) 01507 #define PWR_CR_PLS_2V2 ((uint16_t)0x0000) 01508 #define PWR_CR_PLS_2V3 ((uint16_t)0x0020) 01509 #define PWR_CR_PLS_2V4 ((uint16_t)0x0040) 01510 #define PWR_CR_PLS_2V5 ((uint16_t)0x0060) 01511 #define PWR_CR_PLS_2V6 ((uint16_t)0x0080) 01512 #define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) 01513 #define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) 01514 #define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) 01516 #define PWR_CR_DBP ((uint16_t)0x0100) 01519 /******************* Bit definition for PWR_CSR register ********************/ 01520 #define PWR_CSR_WUF ((uint16_t)0x0001) 01521 #define PWR_CSR_SBF ((uint16_t)0x0002) 01522 #define PWR_CSR_PVDO ((uint16_t)0x0004) 01523 #define PWR_CSR_EWUP ((uint16_t)0x0100) 01525 /******************************************************************************/ 01526 /* */ 01527 /* Backup registers */ 01528 /* */ 01529 /******************************************************************************/ 01530 01531 /******************* Bit definition for BKP_DR1 register ********************/ 01532 #define BKP_DR1_D ((uint16_t)0xFFFF) 01534 /******************* Bit definition for BKP_DR2 register ********************/ 01535 #define BKP_DR2_D ((uint16_t)0xFFFF) 01537 /******************* Bit definition for BKP_DR3 register ********************/ 01538 #define BKP_DR3_D ((uint16_t)0xFFFF) 01540 /******************* Bit definition for BKP_DR4 register ********************/ 01541 #define BKP_DR4_D ((uint16_t)0xFFFF) 01543 /******************* Bit definition for BKP_DR5 register ********************/ 01544 #define BKP_DR5_D ((uint16_t)0xFFFF) 01546 /******************* Bit definition for BKP_DR6 register ********************/ 01547 #define BKP_DR6_D ((uint16_t)0xFFFF) 01549 /******************* Bit definition for BKP_DR7 register ********************/ 01550 #define BKP_DR7_D ((uint16_t)0xFFFF) 01552 /******************* Bit definition for BKP_DR8 register ********************/ 01553 #define BKP_DR8_D ((uint16_t)0xFFFF) 01555 /******************* Bit definition for BKP_DR9 register ********************/ 01556 #define BKP_DR9_D ((uint16_t)0xFFFF) 01558 /******************* Bit definition for BKP_DR10 register *******************/ 01559 #define BKP_DR10_D ((uint16_t)0xFFFF) 01561 /******************* Bit definition for BKP_DR11 register *******************/ 01562 #define BKP_DR11_D ((uint16_t)0xFFFF) 01564 /******************* Bit definition for BKP_DR12 register *******************/ 01565 #define BKP_DR12_D ((uint16_t)0xFFFF) 01567 /******************* Bit definition for BKP_DR13 register *******************/ 01568 #define BKP_DR13_D ((uint16_t)0xFFFF) 01570 /******************* Bit definition for BKP_DR14 register *******************/ 01571 #define BKP_DR14_D ((uint16_t)0xFFFF) 01573 /******************* Bit definition for BKP_DR15 register *******************/ 01574 #define BKP_DR15_D ((uint16_t)0xFFFF) 01576 /******************* Bit definition for BKP_DR16 register *******************/ 01577 #define BKP_DR16_D ((uint16_t)0xFFFF) 01579 /******************* Bit definition for BKP_DR17 register *******************/ 01580 #define BKP_DR17_D ((uint16_t)0xFFFF) 01582 /****************** Bit definition for BKP_DR18 register ********************/ 01583 #define BKP_DR18_D ((uint16_t)0xFFFF) 01585 /******************* Bit definition for BKP_DR19 register *******************/ 01586 #define BKP_DR19_D ((uint16_t)0xFFFF) 01588 /******************* Bit definition for BKP_DR20 register *******************/ 01589 #define BKP_DR20_D ((uint16_t)0xFFFF) 01591 /******************* Bit definition for BKP_DR21 register *******************/ 01592 #define BKP_DR21_D ((uint16_t)0xFFFF) 01594 /******************* Bit definition for BKP_DR22 register *******************/ 01595 #define BKP_DR22_D ((uint16_t)0xFFFF) 01597 /******************* Bit definition for BKP_DR23 register *******************/ 01598 #define BKP_DR23_D ((uint16_t)0xFFFF) 01600 /******************* Bit definition for BKP_DR24 register *******************/ 01601 #define BKP_DR24_D ((uint16_t)0xFFFF) 01603 /******************* Bit definition for BKP_DR25 register *******************/ 01604 #define BKP_DR25_D ((uint16_t)0xFFFF) 01606 /******************* Bit definition for BKP_DR26 register *******************/ 01607 #define BKP_DR26_D ((uint16_t)0xFFFF) 01609 /******************* Bit definition for BKP_DR27 register *******************/ 01610 #define BKP_DR27_D ((uint16_t)0xFFFF) 01612 /******************* Bit definition for BKP_DR28 register *******************/ 01613 #define BKP_DR28_D ((uint16_t)0xFFFF) 01615 /******************* Bit definition for BKP_DR29 register *******************/ 01616 #define BKP_DR29_D ((uint16_t)0xFFFF) 01618 /******************* Bit definition for BKP_DR30 register *******************/ 01619 #define BKP_DR30_D ((uint16_t)0xFFFF) 01621 /******************* Bit definition for BKP_DR31 register *******************/ 01622 #define BKP_DR31_D ((uint16_t)0xFFFF) 01624 /******************* Bit definition for BKP_DR32 register *******************/ 01625 #define BKP_DR32_D ((uint16_t)0xFFFF) 01627 /******************* Bit definition for BKP_DR33 register *******************/ 01628 #define BKP_DR33_D ((uint16_t)0xFFFF) 01630 /******************* Bit definition for BKP_DR34 register *******************/ 01631 #define BKP_DR34_D ((uint16_t)0xFFFF) 01633 /******************* Bit definition for BKP_DR35 register *******************/ 01634 #define BKP_DR35_D ((uint16_t)0xFFFF) 01636 /******************* Bit definition for BKP_DR36 register *******************/ 01637 #define BKP_DR36_D ((uint16_t)0xFFFF) 01639 /******************* Bit definition for BKP_DR37 register *******************/ 01640 #define BKP_DR37_D ((uint16_t)0xFFFF) 01642 /******************* Bit definition for BKP_DR38 register *******************/ 01643 #define BKP_DR38_D ((uint16_t)0xFFFF) 01645 /******************* Bit definition for BKP_DR39 register *******************/ 01646 #define BKP_DR39_D ((uint16_t)0xFFFF) 01648 /******************* Bit definition for BKP_DR40 register *******************/ 01649 #define BKP_DR40_D ((uint16_t)0xFFFF) 01651 /******************* Bit definition for BKP_DR41 register *******************/ 01652 #define BKP_DR41_D ((uint16_t)0xFFFF) 01654 /******************* Bit definition for BKP_DR42 register *******************/ 01655 #define BKP_DR42_D ((uint16_t)0xFFFF) 01657 /****************** Bit definition for BKP_RTCCR register *******************/ 01658 #define BKP_RTCCR_CAL ((uint16_t)0x007F) 01659 #define BKP_RTCCR_CCO ((uint16_t)0x0080) 01660 #define BKP_RTCCR_ASOE ((uint16_t)0x0100) 01661 #define BKP_RTCCR_ASOS ((uint16_t)0x0200) 01663 /******************** Bit definition for BKP_CR register ********************/ 01664 #define BKP_CR_TPE ((uint8_t)0x01) 01665 #define BKP_CR_TPAL ((uint8_t)0x02) 01667 /******************* Bit definition for BKP_CSR register ********************/ 01668 #define BKP_CSR_CTE ((uint16_t)0x0001) 01669 #define BKP_CSR_CTI ((uint16_t)0x0002) 01670 #define BKP_CSR_TPIE ((uint16_t)0x0004) 01671 #define BKP_CSR_TEF ((uint16_t)0x0100) 01672 #define BKP_CSR_TIF ((uint16_t)0x0200) 01674 /******************************************************************************/ 01675 /* */ 01676 /* Reset and Clock Control */ 01677 /* */ 01678 /******************************************************************************/ 01679 01680 /******************** Bit definition for RCC_CR register ********************/ 01681 #define RCC_CR_HSION ((uint32_t)0x00000001) 01682 #define RCC_CR_HSIRDY ((uint32_t)0x00000002) 01683 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8) 01684 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00) 01685 #define RCC_CR_HSEON ((uint32_t)0x00010000) 01686 #define RCC_CR_HSERDY ((uint32_t)0x00020000) 01687 #define RCC_CR_HSEBYP ((uint32_t)0x00040000) 01688 #define RCC_CR_CSSON ((uint32_t)0x00080000) 01689 #define RCC_CR_PLLON ((uint32_t)0x01000000) 01690 #define RCC_CR_PLLRDY ((uint32_t)0x02000000) 01692 #ifdef STM32F10X_CL 01693 #define RCC_CR_PLL2ON ((uint32_t)0x04000000) 01694 #define RCC_CR_PLL2RDY ((uint32_t)0x08000000) 01695 #define RCC_CR_PLL3ON ((uint32_t)0x10000000) 01696 #define RCC_CR_PLL3RDY ((uint32_t)0x20000000) 01697 #endif /* STM32F10X_CL */ 01698 01699 /******************* Bit definition for RCC_CFGR register *******************/ 01701 #define RCC_CFGR_SW ((uint32_t)0x00000003) 01702 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) 01703 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) 01705 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) 01706 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) 01707 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) 01710 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) 01711 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) 01712 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) 01714 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) 01715 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) 01716 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) 01719 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) 01720 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) 01721 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) 01722 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) 01723 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) 01725 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) 01726 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) 01727 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) 01728 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) 01729 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) 01730 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) 01731 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) 01732 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) 01733 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) 01736 #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) 01737 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) 01738 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) 01739 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) 01741 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) 01742 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) 01743 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) 01744 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) 01745 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) 01748 #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) 01749 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) 01750 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) 01751 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) 01753 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) 01754 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) 01755 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) 01756 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) 01757 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) 01760 #define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) 01761 #define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) 01762 #define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) 01764 #define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) 01765 #define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) 01766 #define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) 01767 #define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) 01769 #define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) 01771 #define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) 01774 #define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) 01775 #define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) 01776 #define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) 01777 #define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) 01778 #define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) 01780 #ifdef STM32F10X_CL 01781 #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) 01782 #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) 01784 #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) 01785 #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) 01787 #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) 01788 #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) 01789 #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) 01790 #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) 01791 #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) 01792 #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) 01793 #define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) 01795 #define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) 01798 #define RCC_CFGR_MCO ((uint32_t)0x0F000000) 01799 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) 01800 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) 01801 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) 01802 #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) 01804 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) 01805 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) 01806 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) 01807 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) 01808 #define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000) 01809 #define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) 01810 #define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) 01811 #define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) 01812 #define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) 01813 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) 01814 #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) 01815 #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) 01817 #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) 01818 #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) 01820 #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) 01821 #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) 01822 #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) 01823 #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) 01824 #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) 01825 #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) 01826 #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) 01827 #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) 01828 #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) 01829 #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) 01830 #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) 01831 #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) 01832 #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) 01833 #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) 01834 #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) 01837 #define RCC_CFGR_MCO ((uint32_t)0x07000000) 01838 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) 01839 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) 01840 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) 01842 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) 01843 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) 01844 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) 01845 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) 01846 #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) 01847 #else 01848 #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) 01849 #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) 01851 #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) 01852 #define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) 01854 #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) 01855 #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) 01856 #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) 01857 #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) 01858 #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) 01859 #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) 01860 #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) 01861 #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) 01862 #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) 01863 #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) 01864 #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) 01865 #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) 01866 #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) 01867 #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) 01868 #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) 01869 #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) 01872 #define RCC_CFGR_MCO ((uint32_t)0x07000000) 01873 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) 01874 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) 01875 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) 01877 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) 01878 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) 01879 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) 01880 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) 01881 #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) 01882 #endif /* STM32F10X_CL */ 01883 01885 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) 01886 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) 01887 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) 01888 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) 01889 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) 01890 #define RCC_CIR_CSSF ((uint32_t)0x00000080) 01891 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) 01892 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) 01893 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) 01894 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) 01895 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) 01896 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) 01897 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) 01898 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) 01899 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) 01900 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) 01901 #define RCC_CIR_CSSC ((uint32_t)0x00800000) 01903 #ifdef STM32F10X_CL 01904 #define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) 01905 #define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) 01906 #define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) 01907 #define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) 01908 #define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) 01909 #define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) 01910 #endif /* STM32F10X_CL */ 01911 01912 /***************** Bit definition for RCC_APB2RSTR register *****************/ 01913 #define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) 01914 #define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) 01915 #define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) 01916 #define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) 01917 #define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) 01918 #define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) 01920 #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) 01921 #define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) 01922 #endif 01923 01924 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) 01925 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) 01926 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) 01928 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) 01929 #define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) 01930 #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) 01931 #define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) 01932 #endif 01933 01934 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) 01935 #define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) 01936 #endif /* STM32F10X_LD && STM32F10X_LD_VL */ 01937 01938 #if defined (STM32F10X_HD) || defined (STM32F10X_XL) 01939 #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) 01940 #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) 01941 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) 01942 #define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) 01943 #endif 01944 01945 #if defined (STM32F10X_HD_VL) 01946 #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) 01947 #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) 01948 #endif 01949 01950 #ifdef STM32F10X_XL 01951 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000) 01952 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000) 01953 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000) 01954 #endif /* STM32F10X_XL */ 01955 01956 /***************** Bit definition for RCC_APB1RSTR register *****************/ 01957 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) 01958 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) 01959 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) 01960 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) 01961 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) 01963 #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) 01964 #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) 01965 #endif 01966 01967 #define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) 01968 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) 01970 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) 01971 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) 01972 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) 01973 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) 01974 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) 01975 #endif /* STM32F10X_LD && STM32F10X_LD_VL */ 01976 01977 #if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined (STM32F10X_XL) 01978 #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) 01979 #endif 01980 01981 #if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_XL) 01982 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) 01983 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) 01984 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) 01985 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) 01986 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) 01987 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) 01988 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) 01989 #endif 01990 01991 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) 01992 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) 01993 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) 01994 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) 01995 #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) 01996 #endif 01997 01998 #if defined (STM32F10X_HD_VL) 01999 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) 02000 #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) 02001 #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) 02002 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) 02003 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) 02004 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) 02005 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) 02006 #endif 02007 02008 #ifdef STM32F10X_CL 02009 #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) 02010 #endif /* STM32F10X_CL */ 02011 02012 #ifdef STM32F10X_XL 02013 #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) 02014 #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) 02015 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) 02016 #endif /* STM32F10X_XL */ 02017 02018 /****************** Bit definition for RCC_AHBENR register ******************/ 02019 #define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) 02020 #define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) 02021 #define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) 02022 #define RCC_AHBENR_CRCEN ((uint16_t)0x0040) 02024 #if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_HD_VL) 02025 #define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) 02026 #endif 02027 02028 #if defined (STM32F10X_HD) || defined (STM32F10X_XL) 02029 #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) 02030 #define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) 02031 #endif 02032 02033 #if defined (STM32F10X_HD_VL) 02034 #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) 02035 #endif 02036 02037 #ifdef STM32F10X_CL 02038 #define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) 02039 #define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) 02040 #define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) 02041 #define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) 02042 #endif /* STM32F10X_CL */ 02043 02044 /****************** Bit definition for RCC_APB2ENR register *****************/ 02045 #define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) 02046 #define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) 02047 #define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) 02048 #define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) 02049 #define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) 02050 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) 02052 #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) 02053 #define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) 02054 #endif 02055 02056 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) 02057 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) 02058 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) 02060 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) 02061 #define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) 02062 #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) 02063 #define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) 02064 #endif 02065 02066 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) 02067 #define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) 02068 #endif /* STM32F10X_LD && STM32F10X_LD_VL */ 02069 02070 #if defined (STM32F10X_HD) || defined (STM32F10X_XL) 02071 #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) 02072 #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) 02073 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) 02074 #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) 02075 #endif 02076 02077 #if defined (STM32F10X_HD_VL) 02078 #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) 02079 #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) 02080 #endif 02081 02082 #ifdef STM32F10X_XL 02083 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000) 02084 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000) 02085 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000) 02086 #endif 02087 02088 /***************** Bit definition for RCC_APB1ENR register ******************/ 02089 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) 02090 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) 02091 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) 02092 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) 02093 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) 02095 #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) 02096 #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) 02097 #endif 02098 02099 #define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) 02100 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) 02102 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) 02103 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) 02104 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) 02105 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) 02106 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) 02107 #endif /* STM32F10X_LD && STM32F10X_LD_VL */ 02108 02109 #if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) 02110 #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) 02111 #endif 02112 02113 #if defined (STM32F10X_HD) || defined (STM32F10X_CL) 02114 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) 02115 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) 02116 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) 02117 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) 02118 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) 02119 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) 02120 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) 02121 #endif 02122 02123 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) 02124 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) 02125 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) 02126 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) 02127 #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) 02128 #endif 02129 02130 #ifdef STM32F10X_HD_VL 02131 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) 02132 #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) 02133 #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) 02134 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) 02135 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) 02136 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) 02137 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) 02138 #endif /* STM32F10X_HD_VL */ 02139 02140 #ifdef STM32F10X_CL 02141 #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) 02142 #endif /* STM32F10X_CL */ 02143 02144 #ifdef STM32F10X_XL 02145 #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) 02146 #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) 02147 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) 02148 #endif /* STM32F10X_XL */ 02149 02150 /******************* Bit definition for RCC_BDCR register *******************/ 02151 #define RCC_BDCR_LSEON ((uint32_t)0x00000001) 02152 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) 02153 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) 02155 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) 02156 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) 02157 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) 02160 #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) 02161 #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) 02162 #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) 02163 #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) 02165 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) 02166 #define RCC_BDCR_BDRST ((uint32_t)0x00010000) 02168 /******************* Bit definition for RCC_CSR register ********************/ 02169 #define RCC_CSR_LSION ((uint32_t)0x00000001) 02170 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) 02171 #define RCC_CSR_RMVF ((uint32_t)0x01000000) 02172 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) 02173 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) 02174 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) 02175 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) 02176 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) 02177 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) 02179 #ifdef STM32F10X_CL 02180 /******************* Bit definition for RCC_AHBRSTR register ****************/ 02181 #define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) 02182 #define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) 02184 /******************* Bit definition for RCC_CFGR2 register ******************/ 02185 02186 #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) 02187 #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) 02188 #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) 02189 #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) 02190 #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) 02192 #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) 02193 #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) 02194 #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) 02195 #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) 02196 #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) 02197 #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) 02198 #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) 02199 #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) 02200 #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) 02201 #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) 02202 #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) 02203 #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) 02204 #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) 02205 #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) 02206 #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) 02207 #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) 02210 #define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) 02211 #define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) 02212 #define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) 02213 #define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) 02214 #define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) 02216 #define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) 02217 #define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) 02218 #define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) 02219 #define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) 02220 #define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) 02221 #define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) 02222 #define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) 02223 #define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) 02224 #define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) 02225 #define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) 02226 #define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) 02227 #define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) 02228 #define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) 02229 #define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) 02230 #define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) 02231 #define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) 02234 #define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) 02235 #define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) 02236 #define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) 02237 #define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) 02238 #define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) 02240 #define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) 02241 #define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) 02242 #define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) 02243 #define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) 02244 #define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) 02245 #define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) 02246 #define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) 02247 #define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) 02248 #define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) 02251 #define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) 02252 #define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) 02253 #define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) 02254 #define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) 02255 #define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) 02257 #define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) 02258 #define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) 02259 #define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) 02260 #define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) 02261 #define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) 02262 #define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) 02263 #define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) 02264 #define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) 02265 #define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) 02267 #define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) 02268 #define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) 02269 #define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) 02270 #define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) 02271 #define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) 02272 #endif /* STM32F10X_CL */ 02273 02274 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) 02275 /******************* Bit definition for RCC_CFGR2 register ******************/ 02277 #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) 02278 #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) 02279 #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) 02280 #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) 02281 #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) 02283 #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) 02284 #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) 02285 #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) 02286 #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) 02287 #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) 02288 #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) 02289 #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) 02290 #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) 02291 #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) 02292 #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) 02293 #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) 02294 #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) 02295 #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) 02296 #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) 02297 #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) 02298 #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) 02299 #endif 02300 02301 /******************************************************************************/ 02302 /* */ 02303 /* General Purpose and Alternate Function I/O */ 02304 /* */ 02305 /******************************************************************************/ 02306 02307 /******************* Bit definition for GPIO_CRL register *******************/ 02308 #define GPIO_CRL_MODE ((uint32_t)0x33333333) 02310 #define GPIO_CRL_MODE0 ((uint32_t)0x00000003) 02311 #define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) 02312 #define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) 02314 #define GPIO_CRL_MODE1 ((uint32_t)0x00000030) 02315 #define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) 02316 #define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) 02318 #define GPIO_CRL_MODE2 ((uint32_t)0x00000300) 02319 #define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) 02320 #define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) 02322 #define GPIO_CRL_MODE3 ((uint32_t)0x00003000) 02323 #define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) 02324 #define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) 02326 #define GPIO_CRL_MODE4 ((uint32_t)0x00030000) 02327 #define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) 02328 #define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) 02330 #define GPIO_CRL_MODE5 ((uint32_t)0x00300000) 02331 #define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) 02332 #define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) 02334 #define GPIO_CRL_MODE6 ((uint32_t)0x03000000) 02335 #define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) 02336 #define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) 02338 #define GPIO_CRL_MODE7 ((uint32_t)0x30000000) 02339 #define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) 02340 #define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) 02342 #define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) 02344 #define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) 02345 #define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) 02346 #define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) 02348 #define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) 02349 #define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) 02350 #define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) 02352 #define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) 02353 #define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) 02354 #define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) 02356 #define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) 02357 #define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) 02358 #define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) 02360 #define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) 02361 #define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) 02362 #define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) 02364 #define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) 02365 #define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) 02366 #define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) 02368 #define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) 02369 #define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) 02370 #define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) 02372 #define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) 02373 #define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) 02374 #define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) 02376 /******************* Bit definition for GPIO_CRH register *******************/ 02377 #define GPIO_CRH_MODE ((uint32_t)0x33333333) 02379 #define GPIO_CRH_MODE8 ((uint32_t)0x00000003) 02380 #define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) 02381 #define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) 02383 #define GPIO_CRH_MODE9 ((uint32_t)0x00000030) 02384 #define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) 02385 #define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) 02387 #define GPIO_CRH_MODE10 ((uint32_t)0x00000300) 02388 #define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) 02389 #define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) 02391 #define GPIO_CRH_MODE11 ((uint32_t)0x00003000) 02392 #define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) 02393 #define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) 02395 #define GPIO_CRH_MODE12 ((uint32_t)0x00030000) 02396 #define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) 02397 #define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) 02399 #define GPIO_CRH_MODE13 ((uint32_t)0x00300000) 02400 #define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) 02401 #define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) 02403 #define GPIO_CRH_MODE14 ((uint32_t)0x03000000) 02404 #define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) 02405 #define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) 02407 #define GPIO_CRH_MODE15 ((uint32_t)0x30000000) 02408 #define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) 02409 #define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) 02411 #define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) 02413 #define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) 02414 #define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) 02415 #define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) 02417 #define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) 02418 #define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) 02419 #define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) 02421 #define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) 02422 #define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) 02423 #define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) 02425 #define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) 02426 #define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) 02427 #define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) 02429 #define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) 02430 #define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) 02431 #define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) 02433 #define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) 02434 #define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) 02435 #define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) 02437 #define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) 02438 #define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) 02439 #define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) 02441 #define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) 02442 #define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) 02443 #define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) 02446 #define GPIO_IDR_IDR0 ((uint16_t)0x0001) 02447 #define GPIO_IDR_IDR1 ((uint16_t)0x0002) 02448 #define GPIO_IDR_IDR2 ((uint16_t)0x0004) 02449 #define GPIO_IDR_IDR3 ((uint16_t)0x0008) 02450 #define GPIO_IDR_IDR4 ((uint16_t)0x0010) 02451 #define GPIO_IDR_IDR5 ((uint16_t)0x0020) 02452 #define GPIO_IDR_IDR6 ((uint16_t)0x0040) 02453 #define GPIO_IDR_IDR7 ((uint16_t)0x0080) 02454 #define GPIO_IDR_IDR8 ((uint16_t)0x0100) 02455 #define GPIO_IDR_IDR9 ((uint16_t)0x0200) 02456 #define GPIO_IDR_IDR10 ((uint16_t)0x0400) 02457 #define GPIO_IDR_IDR11 ((uint16_t)0x0800) 02458 #define GPIO_IDR_IDR12 ((uint16_t)0x1000) 02459 #define GPIO_IDR_IDR13 ((uint16_t)0x2000) 02460 #define GPIO_IDR_IDR14 ((uint16_t)0x4000) 02461 #define GPIO_IDR_IDR15 ((uint16_t)0x8000) 02463 /******************* Bit definition for GPIO_ODR register *******************/ 02464 #define GPIO_ODR_ODR0 ((uint16_t)0x0001) 02465 #define GPIO_ODR_ODR1 ((uint16_t)0x0002) 02466 #define GPIO_ODR_ODR2 ((uint16_t)0x0004) 02467 #define GPIO_ODR_ODR3 ((uint16_t)0x0008) 02468 #define GPIO_ODR_ODR4 ((uint16_t)0x0010) 02469 #define GPIO_ODR_ODR5 ((uint16_t)0x0020) 02470 #define GPIO_ODR_ODR6 ((uint16_t)0x0040) 02471 #define GPIO_ODR_ODR7 ((uint16_t)0x0080) 02472 #define GPIO_ODR_ODR8 ((uint16_t)0x0100) 02473 #define GPIO_ODR_ODR9 ((uint16_t)0x0200) 02474 #define GPIO_ODR_ODR10 ((uint16_t)0x0400) 02475 #define GPIO_ODR_ODR11 ((uint16_t)0x0800) 02476 #define GPIO_ODR_ODR12 ((uint16_t)0x1000) 02477 #define GPIO_ODR_ODR13 ((uint16_t)0x2000) 02478 #define GPIO_ODR_ODR14 ((uint16_t)0x4000) 02479 #define GPIO_ODR_ODR15 ((uint16_t)0x8000) 02481 /****************** Bit definition for GPIO_BSRR register *******************/ 02482 #define GPIO_BSRR_BS0 ((uint32_t)0x00000001) 02483 #define GPIO_BSRR_BS1 ((uint32_t)0x00000002) 02484 #define GPIO_BSRR_BS2 ((uint32_t)0x00000004) 02485 #define GPIO_BSRR_BS3 ((uint32_t)0x00000008) 02486 #define GPIO_BSRR_BS4 ((uint32_t)0x00000010) 02487 #define GPIO_BSRR_BS5 ((uint32_t)0x00000020) 02488 #define GPIO_BSRR_BS6 ((uint32_t)0x00000040) 02489 #define GPIO_BSRR_BS7 ((uint32_t)0x00000080) 02490 #define GPIO_BSRR_BS8 ((uint32_t)0x00000100) 02491 #define GPIO_BSRR_BS9 ((uint32_t)0x00000200) 02492 #define GPIO_BSRR_BS10 ((uint32_t)0x00000400) 02493 #define GPIO_BSRR_BS11 ((uint32_t)0x00000800) 02494 #define GPIO_BSRR_BS12 ((uint32_t)0x00001000) 02495 #define GPIO_BSRR_BS13 ((uint32_t)0x00002000) 02496 #define GPIO_BSRR_BS14 ((uint32_t)0x00004000) 02497 #define GPIO_BSRR_BS15 ((uint32_t)0x00008000) 02499 #define GPIO_BSRR_BR0 ((uint32_t)0x00010000) 02500 #define GPIO_BSRR_BR1 ((uint32_t)0x00020000) 02501 #define GPIO_BSRR_BR2 ((uint32_t)0x00040000) 02502 #define GPIO_BSRR_BR3 ((uint32_t)0x00080000) 02503 #define GPIO_BSRR_BR4 ((uint32_t)0x00100000) 02504 #define GPIO_BSRR_BR5 ((uint32_t)0x00200000) 02505 #define GPIO_BSRR_BR6 ((uint32_t)0x00400000) 02506 #define GPIO_BSRR_BR7 ((uint32_t)0x00800000) 02507 #define GPIO_BSRR_BR8 ((uint32_t)0x01000000) 02508 #define GPIO_BSRR_BR9 ((uint32_t)0x02000000) 02509 #define GPIO_BSRR_BR10 ((uint32_t)0x04000000) 02510 #define GPIO_BSRR_BR11 ((uint32_t)0x08000000) 02511 #define GPIO_BSRR_BR12 ((uint32_t)0x10000000) 02512 #define GPIO_BSRR_BR13 ((uint32_t)0x20000000) 02513 #define GPIO_BSRR_BR14 ((uint32_t)0x40000000) 02514 #define GPIO_BSRR_BR15 ((uint32_t)0x80000000) 02516 /******************* Bit definition for GPIO_BRR register *******************/ 02517 #define GPIO_BRR_BR0 ((uint16_t)0x0001) 02518 #define GPIO_BRR_BR1 ((uint16_t)0x0002) 02519 #define GPIO_BRR_BR2 ((uint16_t)0x0004) 02520 #define GPIO_BRR_BR3 ((uint16_t)0x0008) 02521 #define GPIO_BRR_BR4 ((uint16_t)0x0010) 02522 #define GPIO_BRR_BR5 ((uint16_t)0x0020) 02523 #define GPIO_BRR_BR6 ((uint16_t)0x0040) 02524 #define GPIO_BRR_BR7 ((uint16_t)0x0080) 02525 #define GPIO_BRR_BR8 ((uint16_t)0x0100) 02526 #define GPIO_BRR_BR9 ((uint16_t)0x0200) 02527 #define GPIO_BRR_BR10 ((uint16_t)0x0400) 02528 #define GPIO_BRR_BR11 ((uint16_t)0x0800) 02529 #define GPIO_BRR_BR12 ((uint16_t)0x1000) 02530 #define GPIO_BRR_BR13 ((uint16_t)0x2000) 02531 #define GPIO_BRR_BR14 ((uint16_t)0x4000) 02532 #define GPIO_BRR_BR15 ((uint16_t)0x8000) 02534 /****************** Bit definition for GPIO_LCKR register *******************/ 02535 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) 02536 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) 02537 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) 02538 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) 02539 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) 02540 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) 02541 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) 02542 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) 02543 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) 02544 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) 02545 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) 02546 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) 02547 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) 02548 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) 02549 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) 02550 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) 02551 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000) 02553 /*----------------------------------------------------------------------------*/ 02554 02555 /****************** Bit definition for AFIO_EVCR register *******************/ 02556 #define AFIO_EVCR_PIN ((uint8_t)0x0F) 02557 #define AFIO_EVCR_PIN_0 ((uint8_t)0x01) 02558 #define AFIO_EVCR_PIN_1 ((uint8_t)0x02) 02559 #define AFIO_EVCR_PIN_2 ((uint8_t)0x04) 02560 #define AFIO_EVCR_PIN_3 ((uint8_t)0x08) 02563 #define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) 02564 #define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) 02565 #define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) 02566 #define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) 02567 #define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) 02568 #define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) 02569 #define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) 02570 #define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) 02571 #define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) 02572 #define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) 02573 #define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) 02574 #define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) 02575 #define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) 02576 #define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) 02577 #define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) 02578 #define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) 02580 #define AFIO_EVCR_PORT ((uint8_t)0x70) 02581 #define AFIO_EVCR_PORT_0 ((uint8_t)0x10) 02582 #define AFIO_EVCR_PORT_1 ((uint8_t)0x20) 02583 #define AFIO_EVCR_PORT_2 ((uint8_t)0x40) 02586 #define AFIO_EVCR_PORT_PA ((uint8_t)0x00) 02587 #define AFIO_EVCR_PORT_PB ((uint8_t)0x10) 02588 #define AFIO_EVCR_PORT_PC ((uint8_t)0x20) 02589 #define AFIO_EVCR_PORT_PD ((uint8_t)0x30) 02590 #define AFIO_EVCR_PORT_PE ((uint8_t)0x40) 02592 #define AFIO_EVCR_EVOE ((uint8_t)0x80) 02594 /****************** Bit definition for AFIO_MAPR register *******************/ 02595 #define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) 02596 #define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) 02597 #define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) 02598 #define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) 02600 #define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) 02601 #define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) 02602 #define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) 02604 /* USART3_REMAP configuration */ 02605 #define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) 02606 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) 02607 #define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) 02609 #define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) 02610 #define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) 02611 #define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) 02614 #define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) 02615 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) 02616 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) 02618 #define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) 02619 #define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) 02620 #define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) 02623 #define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) 02624 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) 02625 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) 02626 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) 02628 #define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) 02629 #define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) 02630 #define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) 02633 #define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) 02634 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) 02635 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) 02637 #define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) 02639 #define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) 02640 #define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) 02641 #define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) 02644 #define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) 02645 #define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) 02646 #define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) 02648 #define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) 02649 #define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) 02650 #define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) 02651 #define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) 02652 #define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) 02653 #define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) 02656 #define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) 02657 #define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) 02658 #define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) 02659 #define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) 02661 #define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) 02662 #define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) 02663 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) 02664 #define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) 02666 #ifdef STM32F10X_CL 02667 02668 #define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) 02671 #define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) 02674 #define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) 02677 #define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) 02680 #define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) 02683 #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x40000000) 02684 #endif 02685 02686 /***************** Bit definition for AFIO_EXTICR1 register *****************/ 02687 #define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) 02688 #define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) 02689 #define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) 02690 #define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) 02693 #define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) 02694 #define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) 02695 #define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) 02696 #define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) 02697 #define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) 02698 #define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) 02699 #define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) 02702 #define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) 02703 #define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) 02704 #define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) 02705 #define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) 02706 #define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) 02707 #define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) 02708 #define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) 02711 #define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) 02712 #define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) 02713 #define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) 02714 #define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) 02715 #define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) 02716 #define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) 02717 #define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) 02720 #define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) 02721 #define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) 02722 #define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) 02723 #define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) 02724 #define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) 02725 #define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) 02726 #define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) 02728 /***************** Bit definition for AFIO_EXTICR2 register *****************/ 02729 #define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) 02730 #define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) 02731 #define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) 02732 #define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) 02735 #define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) 02736 #define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) 02737 #define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) 02738 #define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) 02739 #define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) 02740 #define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) 02741 #define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) 02743 /* EXTI5 configuration */ 02744 #define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) 02745 #define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) 02746 #define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) 02747 #define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) 02748 #define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) 02749 #define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) 02750 #define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) 02753 #define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) 02754 #define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) 02755 #define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) 02756 #define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) 02757 #define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) 02758 #define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) 02759 #define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) 02762 #define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) 02763 #define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) 02764 #define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) 02765 #define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) 02766 #define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) 02767 #define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) 02768 #define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) 02770 /***************** Bit definition for AFIO_EXTICR3 register *****************/ 02771 #define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) 02772 #define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) 02773 #define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) 02774 #define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) 02777 #define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) 02778 #define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) 02779 #define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) 02780 #define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) 02781 #define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) 02782 #define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) 02783 #define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) 02786 #define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) 02787 #define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) 02788 #define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) 02789 #define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) 02790 #define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) 02791 #define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) 02792 #define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) 02795 #define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) 02796 #define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) 02797 #define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) 02798 #define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) 02799 #define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) 02800 #define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) 02801 #define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) 02804 #define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) 02805 #define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) 02806 #define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) 02807 #define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) 02808 #define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) 02809 #define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) 02810 #define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) 02812 /***************** Bit definition for AFIO_EXTICR4 register *****************/ 02813 #define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) 02814 #define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) 02815 #define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) 02816 #define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) 02818 /* EXTI12 configuration */ 02819 #define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) 02820 #define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) 02821 #define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) 02822 #define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) 02823 #define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) 02824 #define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) 02825 #define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) 02827 /* EXTI13 configuration */ 02828 #define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) 02829 #define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) 02830 #define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) 02831 #define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) 02832 #define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) 02833 #define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) 02834 #define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) 02837 #define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) 02838 #define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) 02839 #define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) 02840 #define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) 02841 #define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) 02842 #define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) 02843 #define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) 02846 #define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) 02847 #define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) 02848 #define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) 02849 #define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) 02850 #define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) 02851 #define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) 02852 #define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) 02854 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) 02855 /****************** Bit definition for AFIO_MAPR2 register ******************/ 02856 #define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) 02857 #define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) 02858 #define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) 02859 #define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) 02860 #define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) 02861 #endif 02862 02863 #ifdef STM32F10X_HD_VL 02864 #define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) 02865 #define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) 02866 #define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) 02867 #define AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800) 02868 #define AFIO_MAPR2_TIM12_REMAP ((uint32_t)0x00001000) 02869 #define AFIO_MAPR2_MISC_REMAP ((uint32_t)0x00002000) 02870 #endif 02871 02872 #ifdef STM32F10X_XL 02873 /****************** Bit definition for AFIO_MAPR2 register ******************/ 02874 #define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) 02875 #define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) 02876 #define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) 02877 #define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) 02878 #define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) 02879 #define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) 02880 #endif 02881 02882 /******************************************************************************/ 02883 /* */ 02884 /* SystemTick */ 02885 /* */ 02886 /******************************************************************************/ 02887 02888 /***************** Bit definition for SysTick_CTRL register *****************/ 02889 #define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) 02890 #define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) 02891 #define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) 02892 #define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) 02894 /***************** Bit definition for SysTick_LOAD register *****************/ 02895 #define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) 02897 /***************** Bit definition for SysTick_VAL register ******************/ 02898 #define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) 02900 /***************** Bit definition for SysTick_CALIB register ****************/ 02901 #define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) 02902 #define SysTick_CALIB_SKEW ((uint32_t)0x40000000) 02903 #define SysTick_CALIB_NOREF ((uint32_t)0x80000000) 02905 /******************************************************************************/ 02906 /* */ 02907 /* Nested Vectored Interrupt Controller */ 02908 /* */ 02909 /******************************************************************************/ 02910 02911 /****************** Bit definition for NVIC_ISER register *******************/ 02912 #define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) 02913 #define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) 02914 #define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) 02915 #define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) 02916 #define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) 02917 #define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) 02918 #define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) 02919 #define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) 02920 #define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) 02921 #define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) 02922 #define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) 02923 #define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) 02924 #define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) 02925 #define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) 02926 #define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) 02927 #define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) 02928 #define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) 02929 #define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) 02930 #define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) 02931 #define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) 02932 #define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) 02933 #define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) 02934 #define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) 02935 #define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) 02936 #define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) 02937 #define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) 02938 #define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) 02939 #define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) 02940 #define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) 02941 #define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) 02942 #define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) 02943 #define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) 02944 #define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) 02946 /****************** Bit definition for NVIC_ICER register *******************/ 02947 #define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) 02948 #define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) 02949 #define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) 02950 #define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) 02951 #define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) 02952 #define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) 02953 #define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) 02954 #define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) 02955 #define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) 02956 #define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) 02957 #define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) 02958 #define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) 02959 #define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) 02960 #define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) 02961 #define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) 02962 #define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) 02963 #define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) 02964 #define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) 02965 #define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) 02966 #define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) 02967 #define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) 02968 #define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) 02969 #define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) 02970 #define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) 02971 #define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) 02972 #define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) 02973 #define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) 02974 #define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) 02975 #define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) 02976 #define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) 02977 #define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) 02978 #define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) 02979 #define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) 02981 /****************** Bit definition for NVIC_ISPR register *******************/ 02982 #define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) 02983 #define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) 02984 #define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) 02985 #define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) 02986 #define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) 02987 #define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) 02988 #define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) 02989 #define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) 02990 #define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) 02991 #define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) 02992 #define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) 02993 #define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) 02994 #define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) 02995 #define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) 02996 #define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) 02997 #define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) 02998 #define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) 02999 #define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) 03000 #define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) 03001 #define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) 03002 #define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) 03003 #define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) 03004 #define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) 03005 #define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) 03006 #define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) 03007 #define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) 03008 #define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) 03009 #define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) 03010 #define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) 03011 #define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) 03012 #define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) 03013 #define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) 03014 #define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) 03016 /****************** Bit definition for NVIC_ICPR register *******************/ 03017 #define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) 03018 #define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) 03019 #define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) 03020 #define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) 03021 #define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) 03022 #define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) 03023 #define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) 03024 #define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) 03025 #define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) 03026 #define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) 03027 #define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) 03028 #define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) 03029 #define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) 03030 #define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) 03031 #define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) 03032 #define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) 03033 #define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) 03034 #define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) 03035 #define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) 03036 #define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) 03037 #define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) 03038 #define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) 03039 #define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) 03040 #define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) 03041 #define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) 03042 #define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) 03043 #define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) 03044 #define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) 03045 #define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) 03046 #define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) 03047 #define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) 03048 #define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) 03049 #define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) 03051 /****************** Bit definition for NVIC_IABR register *******************/ 03052 #define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) 03053 #define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) 03054 #define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) 03055 #define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) 03056 #define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) 03057 #define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) 03058 #define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) 03059 #define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) 03060 #define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) 03061 #define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) 03062 #define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) 03063 #define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) 03064 #define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) 03065 #define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) 03066 #define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) 03067 #define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) 03068 #define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) 03069 #define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) 03070 #define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) 03071 #define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) 03072 #define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) 03073 #define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) 03074 #define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) 03075 #define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) 03076 #define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) 03077 #define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) 03078 #define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) 03079 #define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) 03080 #define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) 03081 #define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) 03082 #define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) 03083 #define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) 03084 #define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) 03086 /****************** Bit definition for NVIC_PRI0 register *******************/ 03087 #define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) 03088 #define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) 03089 #define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) 03090 #define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) 03092 /****************** Bit definition for NVIC_PRI1 register *******************/ 03093 #define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) 03094 #define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) 03095 #define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) 03096 #define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) 03098 /****************** Bit definition for NVIC_PRI2 register *******************/ 03099 #define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) 03100 #define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) 03101 #define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) 03102 #define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) 03104 /****************** Bit definition for NVIC_PRI3 register *******************/ 03105 #define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) 03106 #define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) 03107 #define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) 03108 #define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) 03110 /****************** Bit definition for NVIC_PRI4 register *******************/ 03111 #define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) 03112 #define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) 03113 #define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) 03114 #define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) 03116 /****************** Bit definition for NVIC_PRI5 register *******************/ 03117 #define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) 03118 #define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) 03119 #define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) 03120 #define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) 03122 /****************** Bit definition for NVIC_PRI6 register *******************/ 03123 #define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) 03124 #define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) 03125 #define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) 03126 #define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) 03128 /****************** Bit definition for NVIC_PRI7 register *******************/ 03129 #define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) 03130 #define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) 03131 #define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) 03132 #define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) 03134 /****************** Bit definition for SCB_CPUID register *******************/ 03135 #define SCB_CPUID_REVISION ((uint32_t)0x0000000F) 03136 #define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) 03137 #define SCB_CPUID_Constant ((uint32_t)0x000F0000) 03138 #define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) 03139 #define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) 03141 /******************* Bit definition for SCB_ICSR register *******************/ 03142 #define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) 03143 #define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) 03144 #define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) 03145 #define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) 03146 #define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) 03147 #define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) 03148 #define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) 03149 #define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) 03150 #define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) 03151 #define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) 03153 /******************* Bit definition for SCB_VTOR register *******************/ 03154 #define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) 03155 #define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) 03158 #define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) 03159 #define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) 03160 #define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) 03162 #define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) 03163 #define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) 03164 #define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) 03165 #define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) 03167 /* prority group configuration */ 03168 #define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) 03169 #define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) 03170 #define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) 03171 #define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) 03172 #define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) 03173 #define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) 03174 #define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) 03175 #define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) 03177 #define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) 03178 #define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) 03180 /******************* Bit definition for SCB_SCR register ********************/ 03181 #define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) 03182 #define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) 03183 #define SCB_SCR_SEVONPEND ((uint8_t)0x10) 03185 /******************** Bit definition for SCB_CCR register *******************/ 03186 #define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) 03187 #define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) 03188 #define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) 03189 #define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) 03190 #define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) 03191 #define SCB_CCR_STKALIGN ((uint16_t)0x0200) 03193 /******************* Bit definition for SCB_SHPR register ********************/ 03194 #define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) 03195 #define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) 03196 #define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) 03197 #define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) 03199 /****************** Bit definition for SCB_SHCSR register *******************/ 03200 #define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) 03201 #define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) 03202 #define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) 03203 #define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) 03204 #define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) 03205 #define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) 03206 #define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) 03207 #define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) 03208 #define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) 03209 #define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) 03210 #define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) 03211 #define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) 03212 #define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) 03213 #define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) 03215 /******************* Bit definition for SCB_CFSR register *******************/ 03216 03217 #define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) 03218 #define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) 03219 #define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) 03220 #define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) 03221 #define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) 03223 #define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) 03224 #define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) 03225 #define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) 03226 #define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) 03227 #define SCB_CFSR_STKERR ((uint32_t)0x00001000) 03228 #define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) 03230 #define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) 03231 #define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) 03232 #define SCB_CFSR_INVPC ((uint32_t)0x00040000) 03233 #define SCB_CFSR_NOCP ((uint32_t)0x00080000) 03234 #define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) 03235 #define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) 03237 /******************* Bit definition for SCB_HFSR register *******************/ 03238 #define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) 03239 #define SCB_HFSR_FORCED ((uint32_t)0x40000000) 03240 #define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) 03242 /******************* Bit definition for SCB_DFSR register *******************/ 03243 #define SCB_DFSR_HALTED ((uint8_t)0x01) 03244 #define SCB_DFSR_BKPT ((uint8_t)0x02) 03245 #define SCB_DFSR_DWTTRAP ((uint8_t)0x04) 03246 #define SCB_DFSR_VCATCH ((uint8_t)0x08) 03247 #define SCB_DFSR_EXTERNAL ((uint8_t)0x10) 03249 /******************* Bit definition for SCB_MMFAR register ******************/ 03250 #define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) 03252 /******************* Bit definition for SCB_BFAR register *******************/ 03253 #define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) 03255 /******************* Bit definition for SCB_afsr register *******************/ 03256 #define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) 03258 /******************************************************************************/ 03259 /* */ 03260 /* External Interrupt/Event Controller */ 03261 /* */ 03262 /******************************************************************************/ 03263 03264 /******************* Bit definition for EXTI_IMR register *******************/ 03265 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) 03266 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) 03267 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) 03268 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) 03269 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) 03270 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) 03271 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) 03272 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) 03273 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) 03274 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) 03275 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) 03276 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) 03277 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) 03278 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) 03279 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) 03280 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) 03281 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) 03282 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) 03283 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) 03284 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) 03286 /******************* Bit definition for EXTI_EMR register *******************/ 03287 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) 03288 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) 03289 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) 03290 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) 03291 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) 03292 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) 03293 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) 03294 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) 03295 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) 03296 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) 03297 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) 03298 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) 03299 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) 03300 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) 03301 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) 03302 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) 03303 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) 03304 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) 03305 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) 03306 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) 03308 /****************** Bit definition for EXTI_RTSR register *******************/ 03309 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) 03310 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) 03311 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) 03312 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) 03313 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) 03314 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) 03315 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) 03316 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) 03317 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) 03318 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) 03319 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) 03320 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) 03321 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) 03322 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) 03323 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) 03324 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) 03325 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) 03326 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) 03327 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) 03328 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) 03330 /****************** Bit definition for EXTI_FTSR register *******************/ 03331 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) 03332 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) 03333 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) 03334 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) 03335 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) 03336 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) 03337 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) 03338 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) 03339 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) 03340 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) 03341 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) 03342 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) 03343 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) 03344 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) 03345 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) 03346 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) 03347 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) 03348 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) 03349 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) 03350 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) 03352 /****************** Bit definition for EXTI_SWIER register ******************/ 03353 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) 03354 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) 03355 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) 03356 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) 03357 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) 03358 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) 03359 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) 03360 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) 03361 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) 03362 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) 03363 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) 03364 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) 03365 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) 03366 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) 03367 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) 03368 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) 03369 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) 03370 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) 03371 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) 03372 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) 03374 /******************* Bit definition for EXTI_PR register ********************/ 03375 #define EXTI_PR_PR0 ((uint32_t)0x00000001) 03376 #define EXTI_PR_PR1 ((uint32_t)0x00000002) 03377 #define EXTI_PR_PR2 ((uint32_t)0x00000004) 03378 #define EXTI_PR_PR3 ((uint32_t)0x00000008) 03379 #define EXTI_PR_PR4 ((uint32_t)0x00000010) 03380 #define EXTI_PR_PR5 ((uint32_t)0x00000020) 03381 #define EXTI_PR_PR6 ((uint32_t)0x00000040) 03382 #define EXTI_PR_PR7 ((uint32_t)0x00000080) 03383 #define EXTI_PR_PR8 ((uint32_t)0x00000100) 03384 #define EXTI_PR_PR9 ((uint32_t)0x00000200) 03385 #define EXTI_PR_PR10 ((uint32_t)0x00000400) 03386 #define EXTI_PR_PR11 ((uint32_t)0x00000800) 03387 #define EXTI_PR_PR12 ((uint32_t)0x00001000) 03388 #define EXTI_PR_PR13 ((uint32_t)0x00002000) 03389 #define EXTI_PR_PR14 ((uint32_t)0x00004000) 03390 #define EXTI_PR_PR15 ((uint32_t)0x00008000) 03391 #define EXTI_PR_PR16 ((uint32_t)0x00010000) 03392 #define EXTI_PR_PR17 ((uint32_t)0x00020000) 03393 #define EXTI_PR_PR18 ((uint32_t)0x00040000) 03394 #define EXTI_PR_PR19 ((uint32_t)0x00080000) 03396 /******************************************************************************/ 03397 /* */ 03398 /* DMA Controller */ 03399 /* */ 03400 /******************************************************************************/ 03401 03402 /******************* Bit definition for DMA_ISR register ********************/ 03403 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) 03404 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) 03405 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) 03406 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) 03407 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) 03408 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) 03409 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) 03410 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) 03411 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) 03412 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) 03413 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) 03414 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) 03415 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) 03416 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) 03417 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) 03418 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) 03419 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) 03420 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) 03421 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) 03422 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) 03423 #define DMA_ISR_GIF6 ((uint32_t)0x00100000) 03424 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) 03425 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) 03426 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) 03427 #define DMA_ISR_GIF7 ((uint32_t)0x01000000) 03428 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) 03429 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) 03430 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) 03432 /******************* Bit definition for DMA_IFCR register *******************/ 03433 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) 03434 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) 03435 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) 03436 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) 03437 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) 03438 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) 03439 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) 03440 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) 03441 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) 03442 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) 03443 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) 03444 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) 03445 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) 03446 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) 03447 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) 03448 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) 03449 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) 03450 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) 03451 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) 03452 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) 03453 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) 03454 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) 03455 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) 03456 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) 03457 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) 03458 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) 03459 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) 03460 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) 03462 /******************* Bit definition for DMA_CCR1 register *******************/ 03463 #define DMA_CCR1_EN ((uint16_t)0x0001) 03464 #define DMA_CCR1_TCIE ((uint16_t)0x0002) 03465 #define DMA_CCR1_HTIE ((uint16_t)0x0004) 03466 #define DMA_CCR1_TEIE ((uint16_t)0x0008) 03467 #define DMA_CCR1_DIR ((uint16_t)0x0010) 03468 #define DMA_CCR1_CIRC ((uint16_t)0x0020) 03469 #define DMA_CCR1_PINC ((uint16_t)0x0040) 03470 #define DMA_CCR1_MINC ((uint16_t)0x0080) 03472 #define DMA_CCR1_PSIZE ((uint16_t)0x0300) 03473 #define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) 03474 #define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) 03476 #define DMA_CCR1_MSIZE ((uint16_t)0x0C00) 03477 #define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) 03478 #define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) 03480 #define DMA_CCR1_PL ((uint16_t)0x3000) 03481 #define DMA_CCR1_PL_0 ((uint16_t)0x1000) 03482 #define DMA_CCR1_PL_1 ((uint16_t)0x2000) 03484 #define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) 03486 /******************* Bit definition for DMA_CCR2 register *******************/ 03487 #define DMA_CCR2_EN ((uint16_t)0x0001) 03488 #define DMA_CCR2_TCIE ((uint16_t)0x0002) 03489 #define DMA_CCR2_HTIE ((uint16_t)0x0004) 03490 #define DMA_CCR2_TEIE ((uint16_t)0x0008) 03491 #define DMA_CCR2_DIR ((uint16_t)0x0010) 03492 #define DMA_CCR2_CIRC ((uint16_t)0x0020) 03493 #define DMA_CCR2_PINC ((uint16_t)0x0040) 03494 #define DMA_CCR2_MINC ((uint16_t)0x0080) 03496 #define DMA_CCR2_PSIZE ((uint16_t)0x0300) 03497 #define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) 03498 #define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) 03500 #define DMA_CCR2_MSIZE ((uint16_t)0x0C00) 03501 #define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) 03502 #define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) 03504 #define DMA_CCR2_PL ((uint16_t)0x3000) 03505 #define DMA_CCR2_PL_0 ((uint16_t)0x1000) 03506 #define DMA_CCR2_PL_1 ((uint16_t)0x2000) 03508 #define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) 03510 /******************* Bit definition for DMA_CCR3 register *******************/ 03511 #define DMA_CCR3_EN ((uint16_t)0x0001) 03512 #define DMA_CCR3_TCIE ((uint16_t)0x0002) 03513 #define DMA_CCR3_HTIE ((uint16_t)0x0004) 03514 #define DMA_CCR3_TEIE ((uint16_t)0x0008) 03515 #define DMA_CCR3_DIR ((uint16_t)0x0010) 03516 #define DMA_CCR3_CIRC ((uint16_t)0x0020) 03517 #define DMA_CCR3_PINC ((uint16_t)0x0040) 03518 #define DMA_CCR3_MINC ((uint16_t)0x0080) 03520 #define DMA_CCR3_PSIZE ((uint16_t)0x0300) 03521 #define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) 03522 #define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) 03524 #define DMA_CCR3_MSIZE ((uint16_t)0x0C00) 03525 #define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) 03526 #define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) 03528 #define DMA_CCR3_PL ((uint16_t)0x3000) 03529 #define DMA_CCR3_PL_0 ((uint16_t)0x1000) 03530 #define DMA_CCR3_PL_1 ((uint16_t)0x2000) 03532 #define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) 03535 #define DMA_CCR4_EN ((uint16_t)0x0001) 03536 #define DMA_CCR4_TCIE ((uint16_t)0x0002) 03537 #define DMA_CCR4_HTIE ((uint16_t)0x0004) 03538 #define DMA_CCR4_TEIE ((uint16_t)0x0008) 03539 #define DMA_CCR4_DIR ((uint16_t)0x0010) 03540 #define DMA_CCR4_CIRC ((uint16_t)0x0020) 03541 #define DMA_CCR4_PINC ((uint16_t)0x0040) 03542 #define DMA_CCR4_MINC ((uint16_t)0x0080) 03544 #define DMA_CCR4_PSIZE ((uint16_t)0x0300) 03545 #define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) 03546 #define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) 03548 #define DMA_CCR4_MSIZE ((uint16_t)0x0C00) 03549 #define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) 03550 #define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) 03552 #define DMA_CCR4_PL ((uint16_t)0x3000) 03553 #define DMA_CCR4_PL_0 ((uint16_t)0x1000) 03554 #define DMA_CCR4_PL_1 ((uint16_t)0x2000) 03556 #define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) 03558 /****************** Bit definition for DMA_CCR5 register *******************/ 03559 #define DMA_CCR5_EN ((uint16_t)0x0001) 03560 #define DMA_CCR5_TCIE ((uint16_t)0x0002) 03561 #define DMA_CCR5_HTIE ((uint16_t)0x0004) 03562 #define DMA_CCR5_TEIE ((uint16_t)0x0008) 03563 #define DMA_CCR5_DIR ((uint16_t)0x0010) 03564 #define DMA_CCR5_CIRC ((uint16_t)0x0020) 03565 #define DMA_CCR5_PINC ((uint16_t)0x0040) 03566 #define DMA_CCR5_MINC ((uint16_t)0x0080) 03568 #define DMA_CCR5_PSIZE ((uint16_t)0x0300) 03569 #define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) 03570 #define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) 03572 #define DMA_CCR5_MSIZE ((uint16_t)0x0C00) 03573 #define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) 03574 #define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) 03576 #define DMA_CCR5_PL ((uint16_t)0x3000) 03577 #define DMA_CCR5_PL_0 ((uint16_t)0x1000) 03578 #define DMA_CCR5_PL_1 ((uint16_t)0x2000) 03580 #define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) 03582 /******************* Bit definition for DMA_CCR6 register *******************/ 03583 #define DMA_CCR6_EN ((uint16_t)0x0001) 03584 #define DMA_CCR6_TCIE ((uint16_t)0x0002) 03585 #define DMA_CCR6_HTIE ((uint16_t)0x0004) 03586 #define DMA_CCR6_TEIE ((uint16_t)0x0008) 03587 #define DMA_CCR6_DIR ((uint16_t)0x0010) 03588 #define DMA_CCR6_CIRC ((uint16_t)0x0020) 03589 #define DMA_CCR6_PINC ((uint16_t)0x0040) 03590 #define DMA_CCR6_MINC ((uint16_t)0x0080) 03592 #define DMA_CCR6_PSIZE ((uint16_t)0x0300) 03593 #define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) 03594 #define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) 03596 #define DMA_CCR6_MSIZE ((uint16_t)0x0C00) 03597 #define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) 03598 #define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) 03600 #define DMA_CCR6_PL ((uint16_t)0x3000) 03601 #define DMA_CCR6_PL_0 ((uint16_t)0x1000) 03602 #define DMA_CCR6_PL_1 ((uint16_t)0x2000) 03604 #define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) 03606 /******************* Bit definition for DMA_CCR7 register *******************/ 03607 #define DMA_CCR7_EN ((uint16_t)0x0001) 03608 #define DMA_CCR7_TCIE ((uint16_t)0x0002) 03609 #define DMA_CCR7_HTIE ((uint16_t)0x0004) 03610 #define DMA_CCR7_TEIE ((uint16_t)0x0008) 03611 #define DMA_CCR7_DIR ((uint16_t)0x0010) 03612 #define DMA_CCR7_CIRC ((uint16_t)0x0020) 03613 #define DMA_CCR7_PINC ((uint16_t)0x0040) 03614 #define DMA_CCR7_MINC ((uint16_t)0x0080) 03616 #define DMA_CCR7_PSIZE , ((uint16_t)0x0300) 03617 #define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) 03618 #define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) 03620 #define DMA_CCR7_MSIZE ((uint16_t)0x0C00) 03621 #define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) 03622 #define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) 03624 #define DMA_CCR7_PL ((uint16_t)0x3000) 03625 #define DMA_CCR7_PL_0 ((uint16_t)0x1000) 03626 #define DMA_CCR7_PL_1 ((uint16_t)0x2000) 03628 #define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) 03630 /****************** Bit definition for DMA_CNDTR1 register ******************/ 03631 #define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) 03633 /****************** Bit definition for DMA_CNDTR2 register ******************/ 03634 #define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) 03636 /****************** Bit definition for DMA_CNDTR3 register ******************/ 03637 #define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) 03639 /****************** Bit definition for DMA_CNDTR4 register ******************/ 03640 #define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) 03642 /****************** Bit definition for DMA_CNDTR5 register ******************/ 03643 #define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) 03645 /****************** Bit definition for DMA_CNDTR6 register ******************/ 03646 #define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) 03648 /****************** Bit definition for DMA_CNDTR7 register ******************/ 03649 #define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) 03651 /****************** Bit definition for DMA_CPAR1 register *******************/ 03652 #define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) 03654 /****************** Bit definition for DMA_CPAR2 register *******************/ 03655 #define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) 03657 /****************** Bit definition for DMA_CPAR3 register *******************/ 03658 #define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) 03661 /****************** Bit definition for DMA_CPAR4 register *******************/ 03662 #define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) 03664 /****************** Bit definition for DMA_CPAR5 register *******************/ 03665 #define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) 03667 /****************** Bit definition for DMA_CPAR6 register *******************/ 03668 #define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) 03671 /****************** Bit definition for DMA_CPAR7 register *******************/ 03672 #define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) 03674 /****************** Bit definition for DMA_CMAR1 register *******************/ 03675 #define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) 03677 /****************** Bit definition for DMA_CMAR2 register *******************/ 03678 #define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) 03680 /****************** Bit definition for DMA_CMAR3 register *******************/ 03681 #define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) 03684 /****************** Bit definition for DMA_CMAR4 register *******************/ 03685 #define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) 03687 /****************** Bit definition for DMA_CMAR5 register *******************/ 03688 #define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) 03690 /****************** Bit definition for DMA_CMAR6 register *******************/ 03691 #define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) 03693 /****************** Bit definition for DMA_CMAR7 register *******************/ 03694 #define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) 03696 /******************************************************************************/ 03697 /* */ 03698 /* Analog to Digital Converter */ 03699 /* */ 03700 /******************************************************************************/ 03701 03702 /******************** Bit definition for ADC_SR register ********************/ 03703 #define ADC_SR_AWD ((uint8_t)0x01) 03704 #define ADC_SR_EOC ((uint8_t)0x02) 03705 #define ADC_SR_JEOC ((uint8_t)0x04) 03706 #define ADC_SR_JSTRT ((uint8_t)0x08) 03707 #define ADC_SR_STRT ((uint8_t)0x10) 03709 /******************* Bit definition for ADC_CR1 register ********************/ 03710 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) 03711 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) 03712 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) 03713 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) 03714 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) 03715 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) 03717 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) 03718 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) 03719 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) 03720 #define ADC_CR1_SCAN ((uint32_t)0x00000100) 03721 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) 03722 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) 03723 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) 03724 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) 03726 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) 03727 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) 03728 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) 03729 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) 03731 #define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) 03732 #define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) 03733 #define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) 03734 #define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) 03735 #define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) 03737 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) 03738 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) 03741 /******************* Bit definition for ADC_CR2 register ********************/ 03742 #define ADC_CR2_ADON ((uint32_t)0x00000001) 03743 #define ADC_CR2_CONT ((uint32_t)0x00000002) 03744 #define ADC_CR2_CAL ((uint32_t)0x00000004) 03745 #define ADC_CR2_RSTCAL ((uint32_t)0x00000008) 03746 #define ADC_CR2_DMA ((uint32_t)0x00000100) 03747 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) 03749 #define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) 03750 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) 03751 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) 03752 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) 03754 #define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) 03756 #define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) 03757 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) 03758 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) 03759 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) 03761 #define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) 03762 #define ADC_CR2_JSWSTART ((uint32_t)0x00200000) 03763 #define ADC_CR2_SWSTART ((uint32_t)0x00400000) 03764 #define ADC_CR2_TSVREFE ((uint32_t)0x00800000) 03766 /****************** Bit definition for ADC_SMPR1 register *******************/ 03767 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) 03768 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) 03769 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) 03770 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) 03772 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) 03773 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) 03774 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) 03775 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) 03777 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) 03778 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) 03779 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) 03780 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) 03782 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) 03783 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) 03784 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) 03785 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) 03787 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) 03788 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) 03789 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) 03790 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) 03792 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) 03793 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) 03794 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) 03795 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) 03797 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) 03798 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) 03799 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) 03800 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) 03802 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) 03803 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) 03804 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) 03805 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) 03807 /****************** Bit definition for ADC_SMPR2 register *******************/ 03808 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) 03809 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) 03810 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) 03811 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) 03813 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) 03814 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) 03815 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) 03816 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) 03818 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) 03819 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) 03820 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) 03821 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) 03823 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) 03824 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) 03825 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) 03826 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) 03828 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) 03829 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) 03830 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) 03831 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) 03833 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) 03834 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) 03835 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) 03836 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) 03838 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) 03839 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) 03840 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) 03841 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) 03843 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) 03844 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) 03845 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) 03846 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) 03848 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) 03849 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) 03850 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) 03851 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) 03853 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) 03854 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) 03855 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) 03856 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) 03858 /****************** Bit definition for ADC_JOFR1 register *******************/ 03859 #define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) 03861 /****************** Bit definition for ADC_JOFR2 register *******************/ 03862 #define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) 03864 /****************** Bit definition for ADC_JOFR3 register *******************/ 03865 #define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) 03867 /****************** Bit definition for ADC_JOFR4 register *******************/ 03868 #define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) 03870 /******************* Bit definition for ADC_HTR register ********************/ 03871 #define ADC_HTR_HT ((uint16_t)0x0FFF) 03873 /******************* Bit definition for ADC_LTR register ********************/ 03874 #define ADC_LTR_LT ((uint16_t)0x0FFF) 03876 /******************* Bit definition for ADC_SQR1 register *******************/ 03877 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) 03878 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) 03879 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) 03880 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) 03881 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) 03882 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) 03884 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) 03885 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) 03886 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) 03887 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) 03888 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) 03889 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) 03891 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) 03892 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) 03893 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) 03894 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) 03895 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) 03896 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) 03898 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) 03899 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) 03900 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) 03901 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) 03902 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) 03903 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) 03905 #define ADC_SQR1_L ((uint32_t)0x00F00000) 03906 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) 03907 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) 03908 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) 03909 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) 03911 /******************* Bit definition for ADC_SQR2 register *******************/ 03912 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) 03913 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) 03914 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) 03915 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) 03916 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) 03917 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) 03919 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) 03920 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) 03921 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) 03922 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) 03923 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) 03924 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) 03926 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) 03927 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) 03928 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) 03929 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) 03930 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) 03931 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) 03933 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) 03934 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) 03935 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) 03936 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) 03937 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) 03938 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) 03940 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) 03941 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) 03942 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) 03943 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) 03944 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) 03945 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) 03947 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) 03948 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) 03949 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) 03950 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) 03951 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) 03952 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) 03954 /******************* Bit definition for ADC_SQR3 register *******************/ 03955 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) 03956 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) 03957 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) 03958 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) 03959 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) 03960 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) 03962 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) 03963 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) 03964 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) 03965 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) 03966 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) 03967 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) 03969 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) 03970 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) 03971 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) 03972 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) 03973 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) 03974 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) 03976 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) 03977 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) 03978 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) 03979 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) 03980 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) 03981 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) 03983 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) 03984 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) 03985 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) 03986 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) 03987 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) 03988 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) 03990 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) 03991 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) 03992 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) 03993 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) 03994 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) 03995 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) 03997 /******************* Bit definition for ADC_JSQR register *******************/ 03998 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) 03999 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) 04000 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) 04001 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) 04002 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) 04003 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) 04005 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) 04006 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) 04007 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) 04008 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) 04009 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) 04010 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) 04012 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) 04013 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) 04014 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) 04015 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) 04016 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) 04017 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) 04019 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) 04020 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) 04021 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) 04022 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) 04023 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) 04024 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) 04026 #define ADC_JSQR_JL ((uint32_t)0x00300000) 04027 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) 04028 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) 04030 /******************* Bit definition for ADC_JDR1 register *******************/ 04031 #define ADC_JDR1_JDATA ((uint16_t)0xFFFF) 04033 /******************* Bit definition for ADC_JDR2 register *******************/ 04034 #define ADC_JDR2_JDATA ((uint16_t)0xFFFF) 04036 /******************* Bit definition for ADC_JDR3 register *******************/ 04037 #define ADC_JDR3_JDATA ((uint16_t)0xFFFF) 04039 /******************* Bit definition for ADC_JDR4 register *******************/ 04040 #define ADC_JDR4_JDATA ((uint16_t)0xFFFF) 04042 /******************** Bit definition for ADC_DR register ********************/ 04043 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) 04044 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) 04046 /******************************************************************************/ 04047 /* */ 04048 /* Digital to Analog Converter */ 04049 /* */ 04050 /******************************************************************************/ 04051 04052 /******************** Bit definition for DAC_CR register ********************/ 04053 #define DAC_CR_EN1 ((uint32_t)0x00000001) 04054 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) 04055 #define DAC_CR_TEN1 ((uint32_t)0x00000004) 04057 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) 04058 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) 04059 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) 04060 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) 04062 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) 04063 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) 04064 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) 04066 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) 04067 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) 04068 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) 04069 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) 04070 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) 04072 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) 04073 #define DAC_CR_EN2 ((uint32_t)0x00010000) 04074 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) 04075 #define DAC_CR_TEN2 ((uint32_t)0x00040000) 04077 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) 04078 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) 04079 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) 04080 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) 04082 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) 04083 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) 04084 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) 04086 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) 04087 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) 04088 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) 04089 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) 04090 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) 04092 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) 04094 /***************** Bit definition for DAC_SWTRIGR register ******************/ 04095 #define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) 04096 #define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) 04098 /***************** Bit definition for DAC_DHR12R1 register ******************/ 04099 #define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) 04101 /***************** Bit definition for DAC_DHR12L1 register ******************/ 04102 #define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) 04104 /****************** Bit definition for DAC_DHR8R1 register ******************/ 04105 #define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) 04107 /***************** Bit definition for DAC_DHR12R2 register ******************/ 04108 #define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) 04110 /***************** Bit definition for DAC_DHR12L2 register ******************/ 04111 #define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) 04113 /****************** Bit definition for DAC_DHR8R2 register ******************/ 04114 #define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) 04116 /***************** Bit definition for DAC_DHR12RD register ******************/ 04117 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) 04118 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) 04120 /***************** Bit definition for DAC_DHR12LD register ******************/ 04121 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) 04122 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) 04124 /****************** Bit definition for DAC_DHR8RD register ******************/ 04125 #define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) 04126 #define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) 04128 /******************* Bit definition for DAC_DOR1 register *******************/ 04129 #define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) 04131 /******************* Bit definition for DAC_DOR2 register *******************/ 04132 #define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) 04134 /******************** Bit definition for DAC_SR register ********************/ 04135 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) 04136 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) 04138 /******************************************************************************/ 04139 /* */ 04140 /* CEC */ 04141 /* */ 04142 /******************************************************************************/ 04143 /******************** Bit definition for CEC_CFGR register ******************/ 04144 #define CEC_CFGR_PE ((uint16_t)0x0001) 04145 #define CEC_CFGR_IE ((uint16_t)0x0002) 04146 #define CEC_CFGR_BTEM ((uint16_t)0x0004) 04147 #define CEC_CFGR_BPEM ((uint16_t)0x0008) 04149 /******************** Bit definition for CEC_OAR register ******************/ 04150 #define CEC_OAR_OA ((uint16_t)0x000F) 04151 #define CEC_OAR_OA_0 ((uint16_t)0x0001) 04152 #define CEC_OAR_OA_1 ((uint16_t)0x0002) 04153 #define CEC_OAR_OA_2 ((uint16_t)0x0004) 04154 #define CEC_OAR_OA_3 ((uint16_t)0x0008) 04156 /******************** Bit definition for CEC_PRES register ******************/ 04157 #define CEC_PRES_PRES ((uint16_t)0x3FFF) 04159 /******************** Bit definition for CEC_ESR register ******************/ 04160 #define CEC_ESR_BTE ((uint16_t)0x0001) 04161 #define CEC_ESR_BPE ((uint16_t)0x0002) 04162 #define CEC_ESR_RBTFE ((uint16_t)0x0004) 04163 #define CEC_ESR_SBE ((uint16_t)0x0008) 04164 #define CEC_ESR_ACKE ((uint16_t)0x0010) 04165 #define CEC_ESR_LINE ((uint16_t)0x0020) 04166 #define CEC_ESR_TBTFE ((uint16_t)0x0040) 04168 /******************** Bit definition for CEC_CSR register ******************/ 04169 #define CEC_CSR_TSOM ((uint16_t)0x0001) 04170 #define CEC_CSR_TEOM ((uint16_t)0x0002) 04171 #define CEC_CSR_TERR ((uint16_t)0x0004) 04172 #define CEC_CSR_TBTRF ((uint16_t)0x0008) 04173 #define CEC_CSR_RSOM ((uint16_t)0x0010) 04174 #define CEC_CSR_REOM ((uint16_t)0x0020) 04175 #define CEC_CSR_RERR ((uint16_t)0x0040) 04176 #define CEC_CSR_RBTF ((uint16_t)0x0080) 04178 /******************** Bit definition for CEC_TXD register ******************/ 04179 #define CEC_TXD_TXD ((uint16_t)0x00FF) 04181 /******************** Bit definition for CEC_RXD register ******************/ 04182 #define CEC_RXD_RXD ((uint16_t)0x00FF) 04184 /******************************************************************************/ 04185 /* */ 04186 /* TIM */ 04187 /* */ 04188 /******************************************************************************/ 04189 04190 /******************* Bit definition for TIM_CR1 register ********************/ 04191 #define TIM_CR1_CEN ((uint16_t)0x0001) 04192 #define TIM_CR1_UDIS ((uint16_t)0x0002) 04193 #define TIM_CR1_URS ((uint16_t)0x0004) 04194 #define TIM_CR1_OPM ((uint16_t)0x0008) 04195 #define TIM_CR1_DIR ((uint16_t)0x0010) 04197 #define TIM_CR1_CMS ((uint16_t)0x0060) 04198 #define TIM_CR1_CMS_0 ((uint16_t)0x0020) 04199 #define TIM_CR1_CMS_1 ((uint16_t)0x0040) 04201 #define TIM_CR1_ARPE ((uint16_t)0x0080) 04203 #define TIM_CR1_CKD ((uint16_t)0x0300) 04204 #define TIM_CR1_CKD_0 ((uint16_t)0x0100) 04205 #define TIM_CR1_CKD_1 ((uint16_t)0x0200) 04207 /******************* Bit definition for TIM_CR2 register ********************/ 04208 #define TIM_CR2_CCPC ((uint16_t)0x0001) 04209 #define TIM_CR2_CCUS ((uint16_t)0x0004) 04210 #define TIM_CR2_CCDS ((uint16_t)0x0008) 04212 #define TIM_CR2_MMS ((uint16_t)0x0070) 04213 #define TIM_CR2_MMS_0 ((uint16_t)0x0010) 04214 #define TIM_CR2_MMS_1 ((uint16_t)0x0020) 04215 #define TIM_CR2_MMS_2 ((uint16_t)0x0040) 04217 #define TIM_CR2_TI1S ((uint16_t)0x0080) 04218 #define TIM_CR2_OIS1 ((uint16_t)0x0100) 04219 #define TIM_CR2_OIS1N ((uint16_t)0x0200) 04220 #define TIM_CR2_OIS2 ((uint16_t)0x0400) 04221 #define TIM_CR2_OIS2N ((uint16_t)0x0800) 04222 #define TIM_CR2_OIS3 ((uint16_t)0x1000) 04223 #define TIM_CR2_OIS3N ((uint16_t)0x2000) 04224 #define TIM_CR2_OIS4 ((uint16_t)0x4000) 04226 /******************* Bit definition for TIM_SMCR register *******************/ 04227 #define TIM_SMCR_SMS ((uint16_t)0x0007) 04228 #define TIM_SMCR_SMS_0 ((uint16_t)0x0001) 04229 #define TIM_SMCR_SMS_1 ((uint16_t)0x0002) 04230 #define TIM_SMCR_SMS_2 ((uint16_t)0x0004) 04232 #define TIM_SMCR_TS ((uint16_t)0x0070) 04233 #define TIM_SMCR_TS_0 ((uint16_t)0x0010) 04234 #define TIM_SMCR_TS_1 ((uint16_t)0x0020) 04235 #define TIM_SMCR_TS_2 ((uint16_t)0x0040) 04237 #define TIM_SMCR_MSM ((uint16_t)0x0080) 04239 #define TIM_SMCR_ETF ((uint16_t)0x0F00) 04240 #define TIM_SMCR_ETF_0 ((uint16_t)0x0100) 04241 #define TIM_SMCR_ETF_1 ((uint16_t)0x0200) 04242 #define TIM_SMCR_ETF_2 ((uint16_t)0x0400) 04243 #define TIM_SMCR_ETF_3 ((uint16_t)0x0800) 04245 #define TIM_SMCR_ETPS ((uint16_t)0x3000) 04246 #define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) 04247 #define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) 04249 #define TIM_SMCR_ECE ((uint16_t)0x4000) 04250 #define TIM_SMCR_ETP ((uint16_t)0x8000) 04252 /******************* Bit definition for TIM_DIER register *******************/ 04253 #define TIM_DIER_UIE ((uint16_t)0x0001) 04254 #define TIM_DIER_CC1IE ((uint16_t)0x0002) 04255 #define TIM_DIER_CC2IE ((uint16_t)0x0004) 04256 #define TIM_DIER_CC3IE ((uint16_t)0x0008) 04257 #define TIM_DIER_CC4IE ((uint16_t)0x0010) 04258 #define TIM_DIER_COMIE ((uint16_t)0x0020) 04259 #define TIM_DIER_TIE ((uint16_t)0x0040) 04260 #define TIM_DIER_BIE ((uint16_t)0x0080) 04261 #define TIM_DIER_UDE ((uint16_t)0x0100) 04262 #define TIM_DIER_CC1DE ((uint16_t)0x0200) 04263 #define TIM_DIER_CC2DE ((uint16_t)0x0400) 04264 #define TIM_DIER_CC3DE ((uint16_t)0x0800) 04265 #define TIM_DIER_CC4DE ((uint16_t)0x1000) 04266 #define TIM_DIER_COMDE ((uint16_t)0x2000) 04267 #define TIM_DIER_TDE ((uint16_t)0x4000) 04269 /******************** Bit definition for TIM_SR register ********************/ 04270 #define TIM_SR_UIF ((uint16_t)0x0001) 04271 #define TIM_SR_CC1IF ((uint16_t)0x0002) 04272 #define TIM_SR_CC2IF ((uint16_t)0x0004) 04273 #define TIM_SR_CC3IF ((uint16_t)0x0008) 04274 #define TIM_SR_CC4IF ((uint16_t)0x0010) 04275 #define TIM_SR_COMIF ((uint16_t)0x0020) 04276 #define TIM_SR_TIF ((uint16_t)0x0040) 04277 #define TIM_SR_BIF ((uint16_t)0x0080) 04278 #define TIM_SR_CC1OF ((uint16_t)0x0200) 04279 #define TIM_SR_CC2OF ((uint16_t)0x0400) 04280 #define TIM_SR_CC3OF ((uint16_t)0x0800) 04281 #define TIM_SR_CC4OF ((uint16_t)0x1000) 04283 /******************* Bit definition for TIM_EGR register ********************/ 04284 #define TIM_EGR_UG ((uint8_t)0x01) 04285 #define TIM_EGR_CC1G ((uint8_t)0x02) 04286 #define TIM_EGR_CC2G ((uint8_t)0x04) 04287 #define TIM_EGR_CC3G ((uint8_t)0x08) 04288 #define TIM_EGR_CC4G ((uint8_t)0x10) 04289 #define TIM_EGR_COMG ((uint8_t)0x20) 04290 #define TIM_EGR_TG ((uint8_t)0x40) 04291 #define TIM_EGR_BG ((uint8_t)0x80) 04293 /****************** Bit definition for TIM_CCMR1 register *******************/ 04294 #define TIM_CCMR1_CC1S ((uint16_t)0x0003) 04295 #define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) 04296 #define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) 04298 #define TIM_CCMR1_OC1FE ((uint16_t)0x0004) 04299 #define TIM_CCMR1_OC1PE ((uint16_t)0x0008) 04301 #define TIM_CCMR1_OC1M ((uint16_t)0x0070) 04302 #define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) 04303 #define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) 04304 #define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) 04306 #define TIM_CCMR1_OC1CE ((uint16_t)0x0080) 04308 #define TIM_CCMR1_CC2S ((uint16_t)0x0300) 04309 #define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) 04310 #define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) 04312 #define TIM_CCMR1_OC2FE ((uint16_t)0x0400) 04313 #define TIM_CCMR1_OC2PE ((uint16_t)0x0800) 04315 #define TIM_CCMR1_OC2M ((uint16_t)0x7000) 04316 #define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) 04317 #define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) 04318 #define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) 04320 #define TIM_CCMR1_OC2CE ((uint16_t)0x8000) 04322 /*----------------------------------------------------------------------------*/ 04323 04324 #define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) 04325 #define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) 04326 #define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) 04328 #define TIM_CCMR1_IC1F ((uint16_t)0x00F0) 04329 #define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) 04330 #define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) 04331 #define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) 04332 #define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) 04334 #define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) 04335 #define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) 04336 #define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) 04338 #define TIM_CCMR1_IC2F ((uint16_t)0xF000) 04339 #define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) 04340 #define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) 04341 #define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) 04342 #define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) 04344 /****************** Bit definition for TIM_CCMR2 register *******************/ 04345 #define TIM_CCMR2_CC3S ((uint16_t)0x0003) 04346 #define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) 04347 #define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) 04349 #define TIM_CCMR2_OC3FE ((uint16_t)0x0004) 04350 #define TIM_CCMR2_OC3PE ((uint16_t)0x0008) 04352 #define TIM_CCMR2_OC3M ((uint16_t)0x0070) 04353 #define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) 04354 #define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) 04355 #define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) 04357 #define TIM_CCMR2_OC3CE ((uint16_t)0x0080) 04359 #define TIM_CCMR2_CC4S ((uint16_t)0x0300) 04360 #define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) 04361 #define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) 04363 #define TIM_CCMR2_OC4FE ((uint16_t)0x0400) 04364 #define TIM_CCMR2_OC4PE ((uint16_t)0x0800) 04366 #define TIM_CCMR2_OC4M ((uint16_t)0x7000) 04367 #define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) 04368 #define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) 04369 #define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) 04371 #define TIM_CCMR2_OC4CE ((uint16_t)0x8000) 04373 /*----------------------------------------------------------------------------*/ 04374 04375 #define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) 04376 #define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) 04377 #define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) 04379 #define TIM_CCMR2_IC3F ((uint16_t)0x00F0) 04380 #define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) 04381 #define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) 04382 #define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) 04383 #define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) 04385 #define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) 04386 #define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) 04387 #define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) 04389 #define TIM_CCMR2_IC4F ((uint16_t)0xF000) 04390 #define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) 04391 #define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) 04392 #define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) 04393 #define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) 04395 /******************* Bit definition for TIM_CCER register *******************/ 04396 #define TIM_CCER_CC1E ((uint16_t)0x0001) 04397 #define TIM_CCER_CC1P ((uint16_t)0x0002) 04398 #define TIM_CCER_CC1NE ((uint16_t)0x0004) 04399 #define TIM_CCER_CC1NP ((uint16_t)0x0008) 04400 #define TIM_CCER_CC2E ((uint16_t)0x0010) 04401 #define TIM_CCER_CC2P ((uint16_t)0x0020) 04402 #define TIM_CCER_CC2NE ((uint16_t)0x0040) 04403 #define TIM_CCER_CC2NP ((uint16_t)0x0080) 04404 #define TIM_CCER_CC3E ((uint16_t)0x0100) 04405 #define TIM_CCER_CC3P ((uint16_t)0x0200) 04406 #define TIM_CCER_CC3NE ((uint16_t)0x0400) 04407 #define TIM_CCER_CC3NP ((uint16_t)0x0800) 04408 #define TIM_CCER_CC4E ((uint16_t)0x1000) 04409 #define TIM_CCER_CC4P ((uint16_t)0x2000) 04410 #define TIM_CCER_CC4NP ((uint16_t)0x8000) 04412 /******************* Bit definition for TIM_CNT register ********************/ 04413 #define TIM_CNT_CNT ((uint16_t)0xFFFF) 04415 /******************* Bit definition for TIM_PSC register ********************/ 04416 #define TIM_PSC_PSC ((uint16_t)0xFFFF) 04418 /******************* Bit definition for TIM_ARR register ********************/ 04419 #define TIM_ARR_ARR ((uint16_t)0xFFFF) 04421 /******************* Bit definition for TIM_RCR register ********************/ 04422 #define TIM_RCR_REP ((uint8_t)0xFF) 04424 /******************* Bit definition for TIM_CCR1 register *******************/ 04425 #define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) 04427 /******************* Bit definition for TIM_CCR2 register *******************/ 04428 #define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) 04430 /******************* Bit definition for TIM_CCR3 register *******************/ 04431 #define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) 04433 /******************* Bit definition for TIM_CCR4 register *******************/ 04434 #define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) 04436 /******************* Bit definition for TIM_BDTR register *******************/ 04437 #define TIM_BDTR_DTG ((uint16_t)0x00FF) 04438 #define TIM_BDTR_DTG_0 ((uint16_t)0x0001) 04439 #define TIM_BDTR_DTG_1 ((uint16_t)0x0002) 04440 #define TIM_BDTR_DTG_2 ((uint16_t)0x0004) 04441 #define TIM_BDTR_DTG_3 ((uint16_t)0x0008) 04442 #define TIM_BDTR_DTG_4 ((uint16_t)0x0010) 04443 #define TIM_BDTR_DTG_5 ((uint16_t)0x0020) 04444 #define TIM_BDTR_DTG_6 ((uint16_t)0x0040) 04445 #define TIM_BDTR_DTG_7 ((uint16_t)0x0080) 04447 #define TIM_BDTR_LOCK ((uint16_t)0x0300) 04448 #define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) 04449 #define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) 04451 #define TIM_BDTR_OSSI ((uint16_t)0x0400) 04452 #define TIM_BDTR_OSSR ((uint16_t)0x0800) 04453 #define TIM_BDTR_BKE ((uint16_t)0x1000) 04454 #define TIM_BDTR_BKP ((uint16_t)0x2000) 04455 #define TIM_BDTR_AOE ((uint16_t)0x4000) 04456 #define TIM_BDTR_MOE ((uint16_t)0x8000) 04458 /******************* Bit definition for TIM_DCR register ********************/ 04459 #define TIM_DCR_DBA ((uint16_t)0x001F) 04460 #define TIM_DCR_DBA_0 ((uint16_t)0x0001) 04461 #define TIM_DCR_DBA_1 ((uint16_t)0x0002) 04462 #define TIM_DCR_DBA_2 ((uint16_t)0x0004) 04463 #define TIM_DCR_DBA_3 ((uint16_t)0x0008) 04464 #define TIM_DCR_DBA_4 ((uint16_t)0x0010) 04466 #define TIM_DCR_DBL ((uint16_t)0x1F00) 04467 #define TIM_DCR_DBL_0 ((uint16_t)0x0100) 04468 #define TIM_DCR_DBL_1 ((uint16_t)0x0200) 04469 #define TIM_DCR_DBL_2 ((uint16_t)0x0400) 04470 #define TIM_DCR_DBL_3 ((uint16_t)0x0800) 04471 #define TIM_DCR_DBL_4 ((uint16_t)0x1000) 04473 /******************* Bit definition for TIM_DMAR register *******************/ 04474 #define TIM_DMAR_DMAB ((uint16_t)0xFFFF) 04476 /******************************************************************************/ 04477 /* */ 04478 /* Real-Time Clock */ 04479 /* */ 04480 /******************************************************************************/ 04481 04482 /******************* Bit definition for RTC_CRH register ********************/ 04483 #define RTC_CRH_SECIE ((uint8_t)0x01) 04484 #define RTC_CRH_ALRIE ((uint8_t)0x02) 04485 #define RTC_CRH_OWIE ((uint8_t)0x04) 04487 /******************* Bit definition for RTC_CRL register ********************/ 04488 #define RTC_CRL_SECF ((uint8_t)0x01) 04489 #define RTC_CRL_ALRF ((uint8_t)0x02) 04490 #define RTC_CRL_OWF ((uint8_t)0x04) 04491 #define RTC_CRL_RSF ((uint8_t)0x08) 04492 #define RTC_CRL_CNF ((uint8_t)0x10) 04493 #define RTC_CRL_RTOFF ((uint8_t)0x20) 04495 /******************* Bit definition for RTC_PRLH register *******************/ 04496 #define RTC_PRLH_PRL ((uint16_t)0x000F) 04498 /******************* Bit definition for RTC_PRLL register *******************/ 04499 #define RTC_PRLL_PRL ((uint16_t)0xFFFF) 04501 /******************* Bit definition for RTC_DIVH register *******************/ 04502 #define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) 04504 /******************* Bit definition for RTC_DIVL register *******************/ 04505 #define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) 04507 /******************* Bit definition for RTC_CNTH register *******************/ 04508 #define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) 04510 /******************* Bit definition for RTC_CNTL register *******************/ 04511 #define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) 04513 /******************* Bit definition for RTC_ALRH register *******************/ 04514 #define RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF) 04516 /******************* Bit definition for RTC_ALRL register *******************/ 04517 #define RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF) 04519 /******************************************************************************/ 04520 /* */ 04521 /* Independent WATCHDOG */ 04522 /* */ 04523 /******************************************************************************/ 04524 04525 /******************* Bit definition for IWDG_KR register ********************/ 04526 #define IWDG_KR_KEY ((uint16_t)0xFFFF) 04528 /******************* Bit definition for IWDG_PR register ********************/ 04529 #define IWDG_PR_PR ((uint8_t)0x07) 04530 #define IWDG_PR_PR_0 ((uint8_t)0x01) 04531 #define IWDG_PR_PR_1 ((uint8_t)0x02) 04532 #define IWDG_PR_PR_2 ((uint8_t)0x04) 04534 /******************* Bit definition for IWDG_RLR register *******************/ 04535 #define IWDG_RLR_RL ((uint16_t)0x0FFF) 04537 /******************* Bit definition for IWDG_SR register ********************/ 04538 #define IWDG_SR_PVU ((uint8_t)0x01) 04539 #define IWDG_SR_RVU ((uint8_t)0x02) 04541 /******************************************************************************/ 04542 /* */ 04543 /* Window WATCHDOG */ 04544 /* */ 04545 /******************************************************************************/ 04546 04547 /******************* Bit definition for WWDG_CR register ********************/ 04548 #define WWDG_CR_T ((uint8_t)0x7F) 04549 #define WWDG_CR_T0 ((uint8_t)0x01) 04550 #define WWDG_CR_T1 ((uint8_t)0x02) 04551 #define WWDG_CR_T2 ((uint8_t)0x04) 04552 #define WWDG_CR_T3 ((uint8_t)0x08) 04553 #define WWDG_CR_T4 ((uint8_t)0x10) 04554 #define WWDG_CR_T5 ((uint8_t)0x20) 04555 #define WWDG_CR_T6 ((uint8_t)0x40) 04557 #define WWDG_CR_WDGA ((uint8_t)0x80) 04559 /******************* Bit definition for WWDG_CFR register *******************/ 04560 #define WWDG_CFR_W ((uint16_t)0x007F) 04561 #define WWDG_CFR_W0 ((uint16_t)0x0001) 04562 #define WWDG_CFR_W1 ((uint16_t)0x0002) 04563 #define WWDG_CFR_W2 ((uint16_t)0x0004) 04564 #define WWDG_CFR_W3 ((uint16_t)0x0008) 04565 #define WWDG_CFR_W4 ((uint16_t)0x0010) 04566 #define WWDG_CFR_W5 ((uint16_t)0x0020) 04567 #define WWDG_CFR_W6 ((uint16_t)0x0040) 04569 #define WWDG_CFR_WDGTB ((uint16_t)0x0180) 04570 #define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) 04571 #define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) 04573 #define WWDG_CFR_EWI ((uint16_t)0x0200) 04575 /******************* Bit definition for WWDG_SR register ********************/ 04576 #define WWDG_SR_EWIF ((uint8_t)0x01) 04578 /******************************************************************************/ 04579 /* */ 04580 /* Flexible Static Memory Controller */ 04581 /* */ 04582 /******************************************************************************/ 04583 04584 /****************** Bit definition for FSMC_BCR1 register *******************/ 04585 #define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) 04586 #define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) 04588 #define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) 04589 #define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) 04590 #define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) 04592 #define FSMC_BCR1_MWID ((uint32_t)0x00000030) 04593 #define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) 04594 #define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) 04596 #define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) 04597 #define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) 04598 #define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) 04599 #define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) 04600 #define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) 04601 #define FSMC_BCR1_WREN ((uint32_t)0x00001000) 04602 #define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) 04603 #define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) 04604 #define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) 04605 #define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) 04607 /****************** Bit definition for FSMC_BCR2 register *******************/ 04608 #define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) 04609 #define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) 04611 #define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) 04612 #define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) 04613 #define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) 04615 #define FSMC_BCR2_MWID ((uint32_t)0x00000030) 04616 #define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) 04617 #define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) 04619 #define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) 04620 #define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) 04621 #define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) 04622 #define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) 04623 #define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) 04624 #define FSMC_BCR2_WREN ((uint32_t)0x00001000) 04625 #define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) 04626 #define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) 04627 #define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) 04628 #define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) 04630 /****************** Bit definition for FSMC_BCR3 register *******************/ 04631 #define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) 04632 #define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) 04634 #define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) 04635 #define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) 04636 #define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) 04638 #define FSMC_BCR3_MWID ((uint32_t)0x00000030) 04639 #define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) 04640 #define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) 04642 #define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) 04643 #define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) 04644 #define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) 04645 #define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) 04646 #define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) 04647 #define FSMC_BCR3_WREN ((uint32_t)0x00001000) 04648 #define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) 04649 #define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) 04650 #define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) 04651 #define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) 04653 /****************** Bit definition for FSMC_BCR4 register *******************/ 04654 #define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) 04655 #define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) 04657 #define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) 04658 #define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) 04659 #define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) 04661 #define FSMC_BCR4_MWID ((uint32_t)0x00000030) 04662 #define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) 04663 #define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) 04665 #define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) 04666 #define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) 04667 #define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) 04668 #define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) 04669 #define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) 04670 #define FSMC_BCR4_WREN ((uint32_t)0x00001000) 04671 #define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) 04672 #define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) 04673 #define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) 04674 #define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) 04676 /****************** Bit definition for FSMC_BTR1 register ******************/ 04677 #define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) 04678 #define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) 04679 #define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) 04680 #define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) 04681 #define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) 04683 #define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) 04684 #define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) 04685 #define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) 04686 #define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) 04687 #define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) 04689 #define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) 04690 #define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) 04691 #define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) 04692 #define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) 04693 #define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) 04695 #define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) 04696 #define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) 04697 #define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) 04698 #define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) 04699 #define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) 04701 #define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) 04702 #define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) 04703 #define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) 04704 #define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) 04705 #define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) 04707 #define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) 04708 #define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) 04709 #define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) 04710 #define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) 04711 #define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) 04713 #define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) 04714 #define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) 04715 #define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) 04717 /****************** Bit definition for FSMC_BTR2 register *******************/ 04718 #define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) 04719 #define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) 04720 #define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) 04721 #define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) 04722 #define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) 04724 #define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) 04725 #define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) 04726 #define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) 04727 #define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) 04728 #define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) 04730 #define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) 04731 #define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) 04732 #define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) 04733 #define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) 04734 #define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) 04736 #define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) 04737 #define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) 04738 #define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) 04739 #define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) 04740 #define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) 04742 #define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) 04743 #define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) 04744 #define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) 04745 #define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) 04746 #define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) 04748 #define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) 04749 #define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) 04750 #define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) 04751 #define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) 04752 #define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) 04754 #define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) 04755 #define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) 04756 #define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) 04758 /******************* Bit definition for FSMC_BTR3 register *******************/ 04759 #define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) 04760 #define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) 04761 #define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) 04762 #define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) 04763 #define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) 04765 #define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) 04766 #define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) 04767 #define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) 04768 #define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) 04769 #define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) 04771 #define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) 04772 #define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) 04773 #define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) 04774 #define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) 04775 #define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) 04777 #define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) 04778 #define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) 04779 #define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) 04780 #define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) 04781 #define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) 04783 #define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) 04784 #define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) 04785 #define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) 04786 #define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) 04787 #define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) 04789 #define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) 04790 #define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) 04791 #define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) 04792 #define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) 04793 #define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) 04795 #define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) 04796 #define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) 04797 #define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) 04799 /****************** Bit definition for FSMC_BTR4 register *******************/ 04800 #define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) 04801 #define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) 04802 #define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) 04803 #define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) 04804 #define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) 04806 #define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) 04807 #define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) 04808 #define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) 04809 #define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) 04810 #define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) 04812 #define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) 04813 #define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) 04814 #define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) 04815 #define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) 04816 #define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) 04818 #define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) 04819 #define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) 04820 #define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) 04821 #define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) 04822 #define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) 04824 #define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) 04825 #define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) 04826 #define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) 04827 #define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) 04828 #define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) 04830 #define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) 04831 #define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) 04832 #define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) 04833 #define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) 04834 #define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) 04836 #define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) 04837 #define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) 04838 #define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) 04840 /****************** Bit definition for FSMC_BWTR1 register ******************/ 04841 #define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) 04842 #define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) 04843 #define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) 04844 #define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) 04845 #define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) 04847 #define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) 04848 #define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) 04849 #define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) 04850 #define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) 04851 #define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) 04853 #define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) 04854 #define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) 04855 #define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) 04856 #define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) 04857 #define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) 04859 #define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) 04860 #define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) 04861 #define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) 04862 #define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) 04863 #define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) 04865 #define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) 04866 #define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) 04867 #define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) 04868 #define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) 04869 #define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) 04871 #define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) 04872 #define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) 04873 #define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) 04875 /****************** Bit definition for FSMC_BWTR2 register ******************/ 04876 #define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) 04877 #define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) 04878 #define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) 04879 #define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) 04880 #define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) 04882 #define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) 04883 #define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) 04884 #define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) 04885 #define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) 04886 #define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) 04888 #define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) 04889 #define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) 04890 #define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) 04891 #define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) 04892 #define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) 04894 #define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) 04895 #define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) 04896 #define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) 04897 #define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) 04898 #define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) 04900 #define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) 04901 #define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) 04902 #define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) 04903 #define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) 04904 #define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) 04906 #define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) 04907 #define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) 04908 #define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) 04910 /****************** Bit definition for FSMC_BWTR3 register ******************/ 04911 #define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) 04912 #define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) 04913 #define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) 04914 #define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) 04915 #define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) 04917 #define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) 04918 #define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) 04919 #define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) 04920 #define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) 04921 #define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) 04923 #define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) 04924 #define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) 04925 #define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) 04926 #define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) 04927 #define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) 04929 #define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) 04930 #define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) 04931 #define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) 04932 #define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) 04933 #define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) 04935 #define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) 04936 #define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) 04937 #define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) 04938 #define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) 04939 #define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) 04941 #define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) 04942 #define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) 04943 #define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) 04945 /****************** Bit definition for FSMC_BWTR4 register ******************/ 04946 #define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) 04947 #define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) 04948 #define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) 04949 #define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) 04950 #define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) 04952 #define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) 04953 #define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) 04954 #define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) 04955 #define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) 04956 #define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) 04958 #define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) 04959 #define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) 04960 #define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) 04961 #define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) 04962 #define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) 04964 #define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) 04965 #define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) 04966 #define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) 04967 #define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) 04968 #define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) 04970 #define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) 04971 #define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) 04972 #define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) 04973 #define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) 04974 #define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) 04976 #define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) 04977 #define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) 04978 #define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) 04980 /****************** Bit definition for FSMC_PCR2 register *******************/ 04981 #define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) 04982 #define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) 04983 #define FSMC_PCR2_PTYP ((uint32_t)0x00000008) 04985 #define FSMC_PCR2_PWID ((uint32_t)0x00000030) 04986 #define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) 04987 #define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) 04989 #define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) 04991 #define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) 04992 #define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) 04993 #define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) 04994 #define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) 04995 #define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) 04997 #define FSMC_PCR2_TAR ((uint32_t)0x0001E000) 04998 #define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) 04999 #define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) 05000 #define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) 05001 #define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) 05003 #define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) 05004 #define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) 05005 #define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) 05006 #define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) 05008 /****************** Bit definition for FSMC_PCR3 register *******************/ 05009 #define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) 05010 #define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) 05011 #define FSMC_PCR3_PTYP ((uint32_t)0x00000008) 05013 #define FSMC_PCR3_PWID ((uint32_t)0x00000030) 05014 #define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) 05015 #define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) 05017 #define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) 05019 #define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) 05020 #define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) 05021 #define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) 05022 #define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) 05023 #define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) 05025 #define FSMC_PCR3_TAR ((uint32_t)0x0001E000) 05026 #define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) 05027 #define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) 05028 #define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) 05029 #define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) 05031 #define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) 05032 #define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) 05033 #define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) 05034 #define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) 05036 /****************** Bit definition for FSMC_PCR4 register *******************/ 05037 #define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) 05038 #define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) 05039 #define FSMC_PCR4_PTYP ((uint32_t)0x00000008) 05041 #define FSMC_PCR4_PWID ((uint32_t)0x00000030) 05042 #define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) 05043 #define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) 05045 #define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) 05047 #define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) 05048 #define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) 05049 #define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) 05050 #define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) 05051 #define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) 05053 #define FSMC_PCR4_TAR ((uint32_t)0x0001E000) 05054 #define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) 05055 #define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) 05056 #define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) 05057 #define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) 05059 #define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) 05060 #define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) 05061 #define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) 05062 #define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) 05064 /******************* Bit definition for FSMC_SR2 register *******************/ 05065 #define FSMC_SR2_IRS ((uint8_t)0x01) 05066 #define FSMC_SR2_ILS ((uint8_t)0x02) 05067 #define FSMC_SR2_IFS ((uint8_t)0x04) 05068 #define FSMC_SR2_IREN ((uint8_t)0x08) 05069 #define FSMC_SR2_ILEN ((uint8_t)0x10) 05070 #define FSMC_SR2_IFEN ((uint8_t)0x20) 05071 #define FSMC_SR2_FEMPT ((uint8_t)0x40) 05073 /******************* Bit definition for FSMC_SR3 register *******************/ 05074 #define FSMC_SR3_IRS ((uint8_t)0x01) 05075 #define FSMC_SR3_ILS ((uint8_t)0x02) 05076 #define FSMC_SR3_IFS ((uint8_t)0x04) 05077 #define FSMC_SR3_IREN ((uint8_t)0x08) 05078 #define FSMC_SR3_ILEN ((uint8_t)0x10) 05079 #define FSMC_SR3_IFEN ((uint8_t)0x20) 05080 #define FSMC_SR3_FEMPT ((uint8_t)0x40) 05082 /******************* Bit definition for FSMC_SR4 register *******************/ 05083 #define FSMC_SR4_IRS ((uint8_t)0x01) 05084 #define FSMC_SR4_ILS ((uint8_t)0x02) 05085 #define FSMC_SR4_IFS ((uint8_t)0x04) 05086 #define FSMC_SR4_IREN ((uint8_t)0x08) 05087 #define FSMC_SR4_ILEN ((uint8_t)0x10) 05088 #define FSMC_SR4_IFEN ((uint8_t)0x20) 05089 #define FSMC_SR4_FEMPT ((uint8_t)0x40) 05091 /****************** Bit definition for FSMC_PMEM2 register ******************/ 05092 #define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) 05093 #define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) 05094 #define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) 05095 #define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) 05096 #define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) 05097 #define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) 05098 #define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) 05099 #define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) 05100 #define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) 05102 #define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) 05103 #define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) 05104 #define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) 05105 #define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) 05106 #define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) 05107 #define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) 05108 #define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) 05109 #define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) 05110 #define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) 05112 #define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) 05113 #define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) 05114 #define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) 05115 #define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) 05116 #define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) 05117 #define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) 05118 #define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) 05119 #define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) 05120 #define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) 05122 #define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) 05123 #define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) 05124 #define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) 05125 #define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) 05126 #define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) 05127 #define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) 05128 #define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) 05129 #define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) 05130 #define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) 05132 /****************** Bit definition for FSMC_PMEM3 register ******************/ 05133 #define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) 05134 #define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) 05135 #define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) 05136 #define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) 05137 #define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) 05138 #define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) 05139 #define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) 05140 #define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) 05141 #define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) 05143 #define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) 05144 #define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) 05145 #define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) 05146 #define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) 05147 #define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) 05148 #define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) 05149 #define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) 05150 #define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) 05151 #define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) 05153 #define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) 05154 #define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) 05155 #define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) 05156 #define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) 05157 #define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) 05158 #define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) 05159 #define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) 05160 #define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) 05161 #define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) 05163 #define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) 05164 #define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) 05165 #define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) 05166 #define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) 05167 #define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) 05168 #define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) 05169 #define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) 05170 #define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) 05171 #define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) 05173 /****************** Bit definition for FSMC_PMEM4 register ******************/ 05174 #define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) 05175 #define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) 05176 #define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) 05177 #define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) 05178 #define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) 05179 #define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) 05180 #define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) 05181 #define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) 05182 #define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) 05184 #define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) 05185 #define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) 05186 #define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) 05187 #define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) 05188 #define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) 05189 #define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) 05190 #define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) 05191 #define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) 05192 #define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) 05194 #define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) 05195 #define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) 05196 #define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) 05197 #define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) 05198 #define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) 05199 #define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) 05200 #define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) 05201 #define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) 05202 #define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) 05204 #define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) 05205 #define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) 05206 #define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) 05207 #define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) 05208 #define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) 05209 #define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) 05210 #define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) 05211 #define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) 05212 #define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) 05214 /****************** Bit definition for FSMC_PATT2 register ******************/ 05215 #define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) 05216 #define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) 05217 #define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) 05218 #define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) 05219 #define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) 05220 #define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) 05221 #define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) 05222 #define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) 05223 #define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) 05225 #define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) 05226 #define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) 05227 #define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) 05228 #define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) 05229 #define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) 05230 #define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) 05231 #define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) 05232 #define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) 05233 #define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) 05235 #define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) 05236 #define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) 05237 #define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) 05238 #define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) 05239 #define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) 05240 #define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) 05241 #define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) 05242 #define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) 05243 #define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) 05245 #define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) 05246 #define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) 05247 #define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) 05248 #define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) 05249 #define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) 05250 #define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) 05251 #define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) 05252 #define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) 05253 #define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) 05255 /****************** Bit definition for FSMC_PATT3 register ******************/ 05256 #define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) 05257 #define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) 05258 #define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) 05259 #define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) 05260 #define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) 05261 #define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) 05262 #define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) 05263 #define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) 05264 #define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) 05266 #define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) 05267 #define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) 05268 #define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) 05269 #define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) 05270 #define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) 05271 #define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) 05272 #define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) 05273 #define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) 05274 #define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) 05276 #define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) 05277 #define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) 05278 #define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) 05279 #define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) 05280 #define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) 05281 #define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) 05282 #define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) 05283 #define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) 05284 #define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) 05286 #define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) 05287 #define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) 05288 #define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) 05289 #define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) 05290 #define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) 05291 #define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) 05292 #define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) 05293 #define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) 05294 #define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) 05296 /****************** Bit definition for FSMC_PATT4 register ******************/ 05297 #define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) 05298 #define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) 05299 #define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) 05300 #define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) 05301 #define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) 05302 #define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) 05303 #define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) 05304 #define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) 05305 #define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) 05307 #define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) 05308 #define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) 05309 #define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) 05310 #define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) 05311 #define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) 05312 #define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) 05313 #define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) 05314 #define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) 05315 #define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) 05317 #define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) 05318 #define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) 05319 #define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) 05320 #define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) 05321 #define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) 05322 #define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) 05323 #define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) 05324 #define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) 05325 #define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) 05327 #define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) 05328 #define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) 05329 #define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) 05330 #define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) 05331 #define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) 05332 #define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) 05333 #define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) 05334 #define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) 05335 #define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) 05337 /****************** Bit definition for FSMC_PIO4 register *******************/ 05338 #define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) 05339 #define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) 05340 #define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) 05341 #define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) 05342 #define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) 05343 #define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) 05344 #define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) 05345 #define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) 05346 #define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) 05348 #define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) 05349 #define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) 05350 #define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) 05351 #define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) 05352 #define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) 05353 #define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) 05354 #define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) 05355 #define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) 05356 #define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) 05358 #define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) 05359 #define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) 05360 #define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) 05361 #define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) 05362 #define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) 05363 #define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) 05364 #define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) 05365 #define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) 05366 #define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) 05368 #define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) 05369 #define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) 05370 #define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) 05371 #define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) 05372 #define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) 05373 #define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) 05374 #define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) 05375 #define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) 05376 #define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) 05378 /****************** Bit definition for FSMC_ECCR2 register ******************/ 05379 #define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) 05381 /****************** Bit definition for FSMC_ECCR3 register ******************/ 05382 #define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) 05384 /******************************************************************************/ 05385 /* */ 05386 /* SD host Interface */ 05387 /* */ 05388 /******************************************************************************/ 05389 05390 /****************** Bit definition for SDIO_POWER register ******************/ 05391 #define SDIO_POWER_PWRCTRL ((uint8_t)0x03) 05392 #define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) 05393 #define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) 05395 /****************** Bit definition for SDIO_CLKCR register ******************/ 05396 #define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) 05397 #define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) 05398 #define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) 05399 #define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) 05401 #define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) 05402 #define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) 05403 #define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) 05405 #define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) 05406 #define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) 05408 /******************* Bit definition for SDIO_ARG register *******************/ 05409 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) 05411 /******************* Bit definition for SDIO_CMD register *******************/ 05412 #define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) 05414 #define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) 05415 #define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) 05416 #define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) 05418 #define SDIO_CMD_WAITINT ((uint16_t)0x0100) 05419 #define SDIO_CMD_WAITPEND ((uint16_t)0x0200) 05420 #define SDIO_CMD_CPSMEN ((uint16_t)0x0400) 05421 #define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) 05422 #define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) 05423 #define SDIO_CMD_NIEN ((uint16_t)0x2000) 05424 #define SDIO_CMD_CEATACMD ((uint16_t)0x4000) 05426 /***************** Bit definition for SDIO_RESPCMD register *****************/ 05427 #define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) 05429 /****************** Bit definition for SDIO_RESP0 register ******************/ 05430 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) 05432 /****************** Bit definition for SDIO_RESP1 register ******************/ 05433 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) 05435 /****************** Bit definition for SDIO_RESP2 register ******************/ 05436 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) 05438 /****************** Bit definition for SDIO_RESP3 register ******************/ 05439 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) 05441 /****************** Bit definition for SDIO_RESP4 register ******************/ 05442 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) 05444 /****************** Bit definition for SDIO_DTIMER register *****************/ 05445 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) 05447 /****************** Bit definition for SDIO_DLEN register *******************/ 05448 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) 05450 /****************** Bit definition for SDIO_DCTRL register ******************/ 05451 #define SDIO_DCTRL_DTEN ((uint16_t)0x0001) 05452 #define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) 05453 #define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) 05454 #define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) 05456 #define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) 05457 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) 05458 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) 05459 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) 05460 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) 05462 #define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) 05463 #define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) 05464 #define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) 05465 #define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) 05467 /****************** Bit definition for SDIO_DCOUNT register *****************/ 05468 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) 05470 /****************** Bit definition for SDIO_STA register ********************/ 05471 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) 05472 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) 05473 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) 05474 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) 05475 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) 05476 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) 05477 #define SDIO_STA_CMDREND ((uint32_t)0x00000040) 05478 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) 05479 #define SDIO_STA_DATAEND ((uint32_t)0x00000100) 05480 #define SDIO_STA_STBITERR ((uint32_t)0x00000200) 05481 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) 05482 #define SDIO_STA_CMDACT ((uint32_t)0x00000800) 05483 #define SDIO_STA_TXACT ((uint32_t)0x00001000) 05484 #define SDIO_STA_RXACT ((uint32_t)0x00002000) 05485 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) 05486 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) 05487 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) 05488 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) 05489 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) 05490 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) 05491 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) 05492 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) 05493 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) 05494 #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) 05496 /******************* Bit definition for SDIO_ICR register *******************/ 05497 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) 05498 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) 05499 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) 05500 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) 05501 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) 05502 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) 05503 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) 05504 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) 05505 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) 05506 #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) 05507 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) 05508 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) 05509 #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) 05511 /****************** Bit definition for SDIO_MASK register *******************/ 05512 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) 05513 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) 05514 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) 05515 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) 05516 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) 05517 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) 05518 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) 05519 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) 05520 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) 05521 #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) 05522 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) 05523 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) 05524 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) 05525 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) 05526 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) 05527 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) 05528 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) 05529 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) 05530 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) 05531 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) 05532 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) 05533 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) 05534 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) 05535 #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) 05537 /***************** Bit definition for SDIO_FIFOCNT register *****************/ 05538 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) 05540 /****************** Bit definition for SDIO_FIFO register *******************/ 05541 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) 05543 /******************************************************************************/ 05544 /* */ 05545 /* USB Device FS */ 05546 /* */ 05547 /******************************************************************************/ 05548 05550 /******************* Bit definition for USB_EP0R register *******************/ 05551 #define USB_EP0R_EA ((uint16_t)0x000F) 05553 #define USB_EP0R_STAT_TX ((uint16_t)0x0030) 05554 #define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) 05555 #define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) 05557 #define USB_EP0R_DTOG_TX ((uint16_t)0x0040) 05558 #define USB_EP0R_CTR_TX ((uint16_t)0x0080) 05559 #define USB_EP0R_EP_KIND ((uint16_t)0x0100) 05561 #define USB_EP0R_EP_TYPE ((uint16_t)0x0600) 05562 #define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) 05563 #define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) 05565 #define USB_EP0R_SETUP ((uint16_t)0x0800) 05567 #define USB_EP0R_STAT_RX ((uint16_t)0x3000) 05568 #define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) 05569 #define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) 05571 #define USB_EP0R_DTOG_RX ((uint16_t)0x4000) 05572 #define USB_EP0R_CTR_RX ((uint16_t)0x8000) 05574 /******************* Bit definition for USB_EP1R register *******************/ 05575 #define USB_EP1R_EA ((uint16_t)0x000F) 05577 #define USB_EP1R_STAT_TX ((uint16_t)0x0030) 05578 #define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) 05579 #define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) 05581 #define USB_EP1R_DTOG_TX ((uint16_t)0x0040) 05582 #define USB_EP1R_CTR_TX ((uint16_t)0x0080) 05583 #define USB_EP1R_EP_KIND ((uint16_t)0x0100) 05585 #define USB_EP1R_EP_TYPE ((uint16_t)0x0600) 05586 #define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) 05587 #define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) 05589 #define USB_EP1R_SETUP ((uint16_t)0x0800) 05591 #define USB_EP1R_STAT_RX ((uint16_t)0x3000) 05592 #define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) 05593 #define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) 05595 #define USB_EP1R_DTOG_RX ((uint16_t)0x4000) 05596 #define USB_EP1R_CTR_RX ((uint16_t)0x8000) 05598 /******************* Bit definition for USB_EP2R register *******************/ 05599 #define USB_EP2R_EA ((uint16_t)0x000F) 05601 #define USB_EP2R_STAT_TX ((uint16_t)0x0030) 05602 #define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) 05603 #define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) 05605 #define USB_EP2R_DTOG_TX ((uint16_t)0x0040) 05606 #define USB_EP2R_CTR_TX ((uint16_t)0x0080) 05607 #define USB_EP2R_EP_KIND ((uint16_t)0x0100) 05609 #define USB_EP2R_EP_TYPE ((uint16_t)0x0600) 05610 #define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) 05611 #define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) 05613 #define USB_EP2R_SETUP ((uint16_t)0x0800) 05615 #define USB_EP2R_STAT_RX ((uint16_t)0x3000) 05616 #define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) 05617 #define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) 05619 #define USB_EP2R_DTOG_RX ((uint16_t)0x4000) 05620 #define USB_EP2R_CTR_RX ((uint16_t)0x8000) 05622 /******************* Bit definition for USB_EP3R register *******************/ 05623 #define USB_EP3R_EA ((uint16_t)0x000F) 05625 #define USB_EP3R_STAT_TX ((uint16_t)0x0030) 05626 #define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) 05627 #define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) 05629 #define USB_EP3R_DTOG_TX ((uint16_t)0x0040) 05630 #define USB_EP3R_CTR_TX ((uint16_t)0x0080) 05631 #define USB_EP3R_EP_KIND ((uint16_t)0x0100) 05633 #define USB_EP3R_EP_TYPE ((uint16_t)0x0600) 05634 #define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) 05635 #define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) 05637 #define USB_EP3R_SETUP ((uint16_t)0x0800) 05639 #define USB_EP3R_STAT_RX ((uint16_t)0x3000) 05640 #define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) 05641 #define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) 05643 #define USB_EP3R_DTOG_RX ((uint16_t)0x4000) 05644 #define USB_EP3R_CTR_RX ((uint16_t)0x8000) 05646 /******************* Bit definition for USB_EP4R register *******************/ 05647 #define USB_EP4R_EA ((uint16_t)0x000F) 05649 #define USB_EP4R_STAT_TX ((uint16_t)0x0030) 05650 #define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) 05651 #define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) 05653 #define USB_EP4R_DTOG_TX ((uint16_t)0x0040) 05654 #define USB_EP4R_CTR_TX ((uint16_t)0x0080) 05655 #define USB_EP4R_EP_KIND ((uint16_t)0x0100) 05657 #define USB_EP4R_EP_TYPE ((uint16_t)0x0600) 05658 #define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) 05659 #define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) 05661 #define USB_EP4R_SETUP ((uint16_t)0x0800) 05663 #define USB_EP4R_STAT_RX ((uint16_t)0x3000) 05664 #define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) 05665 #define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) 05667 #define USB_EP4R_DTOG_RX ((uint16_t)0x4000) 05668 #define USB_EP4R_CTR_RX ((uint16_t)0x8000) 05670 /******************* Bit definition for USB_EP5R register *******************/ 05671 #define USB_EP5R_EA ((uint16_t)0x000F) 05673 #define USB_EP5R_STAT_TX ((uint16_t)0x0030) 05674 #define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) 05675 #define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) 05677 #define USB_EP5R_DTOG_TX ((uint16_t)0x0040) 05678 #define USB_EP5R_CTR_TX ((uint16_t)0x0080) 05679 #define USB_EP5R_EP_KIND ((uint16_t)0x0100) 05681 #define USB_EP5R_EP_TYPE ((uint16_t)0x0600) 05682 #define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) 05683 #define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) 05685 #define USB_EP5R_SETUP ((uint16_t)0x0800) 05687 #define USB_EP5R_STAT_RX ((uint16_t)0x3000) 05688 #define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) 05689 #define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) 05691 #define USB_EP5R_DTOG_RX ((uint16_t)0x4000) 05692 #define USB_EP5R_CTR_RX ((uint16_t)0x8000) 05694 /******************* Bit definition for USB_EP6R register *******************/ 05695 #define USB_EP6R_EA ((uint16_t)0x000F) 05697 #define USB_EP6R_STAT_TX ((uint16_t)0x0030) 05698 #define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) 05699 #define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) 05701 #define USB_EP6R_DTOG_TX ((uint16_t)0x0040) 05702 #define USB_EP6R_CTR_TX ((uint16_t)0x0080) 05703 #define USB_EP6R_EP_KIND ((uint16_t)0x0100) 05705 #define USB_EP6R_EP_TYPE ((uint16_t)0x0600) 05706 #define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) 05707 #define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) 05709 #define USB_EP6R_SETUP ((uint16_t)0x0800) 05711 #define USB_EP6R_STAT_RX ((uint16_t)0x3000) 05712 #define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) 05713 #define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) 05715 #define USB_EP6R_DTOG_RX ((uint16_t)0x4000) 05716 #define USB_EP6R_CTR_RX ((uint16_t)0x8000) 05718 /******************* Bit definition for USB_EP7R register *******************/ 05719 #define USB_EP7R_EA ((uint16_t)0x000F) 05721 #define USB_EP7R_STAT_TX ((uint16_t)0x0030) 05722 #define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) 05723 #define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) 05725 #define USB_EP7R_DTOG_TX ((uint16_t)0x0040) 05726 #define USB_EP7R_CTR_TX ((uint16_t)0x0080) 05727 #define USB_EP7R_EP_KIND ((uint16_t)0x0100) 05729 #define USB_EP7R_EP_TYPE ((uint16_t)0x0600) 05730 #define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) 05731 #define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) 05733 #define USB_EP7R_SETUP ((uint16_t)0x0800) 05735 #define USB_EP7R_STAT_RX ((uint16_t)0x3000) 05736 #define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) 05737 #define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) 05739 #define USB_EP7R_DTOG_RX ((uint16_t)0x4000) 05740 #define USB_EP7R_CTR_RX ((uint16_t)0x8000) 05743 /******************* Bit definition for USB_CNTR register *******************/ 05744 #define USB_CNTR_FRES ((uint16_t)0x0001) 05745 #define USB_CNTR_PDWN ((uint16_t)0x0002) 05746 #define USB_CNTR_LP_MODE ((uint16_t)0x0004) 05747 #define USB_CNTR_FSUSP ((uint16_t)0x0008) 05748 #define USB_CNTR_RESUME ((uint16_t)0x0010) 05749 #define USB_CNTR_ESOFM ((uint16_t)0x0100) 05750 #define USB_CNTR_SOFM ((uint16_t)0x0200) 05751 #define USB_CNTR_RESETM ((uint16_t)0x0400) 05752 #define USB_CNTR_SUSPM ((uint16_t)0x0800) 05753 #define USB_CNTR_WKUPM ((uint16_t)0x1000) 05754 #define USB_CNTR_ERRM ((uint16_t)0x2000) 05755 #define USB_CNTR_PMAOVRM ((uint16_t)0x4000) 05756 #define USB_CNTR_CTRM ((uint16_t)0x8000) 05758 /******************* Bit definition for USB_ISTR register *******************/ 05759 #define USB_ISTR_EP_ID ((uint16_t)0x000F) 05760 #define USB_ISTR_DIR ((uint16_t)0x0010) 05761 #define USB_ISTR_ESOF ((uint16_t)0x0100) 05762 #define USB_ISTR_SOF ((uint16_t)0x0200) 05763 #define USB_ISTR_RESET ((uint16_t)0x0400) 05764 #define USB_ISTR_SUSP ((uint16_t)0x0800) 05765 #define USB_ISTR_WKUP ((uint16_t)0x1000) 05766 #define USB_ISTR_ERR ((uint16_t)0x2000) 05767 #define USB_ISTR_PMAOVR ((uint16_t)0x4000) 05768 #define USB_ISTR_CTR ((uint16_t)0x8000) 05770 /******************* Bit definition for USB_FNR register ********************/ 05771 #define USB_FNR_FN ((uint16_t)0x07FF) 05772 #define USB_FNR_LSOF ((uint16_t)0x1800) 05773 #define USB_FNR_LCK ((uint16_t)0x2000) 05774 #define USB_FNR_RXDM ((uint16_t)0x4000) 05775 #define USB_FNR_RXDP ((uint16_t)0x8000) 05777 /****************** Bit definition for USB_DADDR register *******************/ 05778 #define USB_DADDR_ADD ((uint8_t)0x7F) 05779 #define USB_DADDR_ADD0 ((uint8_t)0x01) 05780 #define USB_DADDR_ADD1 ((uint8_t)0x02) 05781 #define USB_DADDR_ADD2 ((uint8_t)0x04) 05782 #define USB_DADDR_ADD3 ((uint8_t)0x08) 05783 #define USB_DADDR_ADD4 ((uint8_t)0x10) 05784 #define USB_DADDR_ADD5 ((uint8_t)0x20) 05785 #define USB_DADDR_ADD6 ((uint8_t)0x40) 05787 #define USB_DADDR_EF ((uint8_t)0x80) 05789 /****************** Bit definition for USB_BTABLE register ******************/ 05790 #define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) 05793 /***************** Bit definition for USB_ADDR0_TX register *****************/ 05794 #define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) 05796 /***************** Bit definition for USB_ADDR1_TX register *****************/ 05797 #define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) 05799 /***************** Bit definition for USB_ADDR2_TX register *****************/ 05800 #define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) 05802 /***************** Bit definition for USB_ADDR3_TX register *****************/ 05803 #define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) 05805 /***************** Bit definition for USB_ADDR4_TX register *****************/ 05806 #define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) 05808 /***************** Bit definition for USB_ADDR5_TX register *****************/ 05809 #define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) 05811 /***************** Bit definition for USB_ADDR6_TX register *****************/ 05812 #define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) 05814 /***************** Bit definition for USB_ADDR7_TX register *****************/ 05815 #define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) 05817 /*----------------------------------------------------------------------------*/ 05818 05819 /***************** Bit definition for USB_COUNT0_TX register ****************/ 05820 #define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) 05822 /***************** Bit definition for USB_COUNT1_TX register ****************/ 05823 #define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) 05825 /***************** Bit definition for USB_COUNT2_TX register ****************/ 05826 #define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) 05828 /***************** Bit definition for USB_COUNT3_TX register ****************/ 05829 #define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) 05831 /***************** Bit definition for USB_COUNT4_TX register ****************/ 05832 #define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) 05834 /***************** Bit definition for USB_COUNT5_TX register ****************/ 05835 #define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) 05837 /***************** Bit definition for USB_COUNT6_TX register ****************/ 05838 #define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) 05840 /***************** Bit definition for USB_COUNT7_TX register ****************/ 05841 #define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) 05843 /*----------------------------------------------------------------------------*/ 05844 05845 /**************** Bit definition for USB_COUNT0_TX_0 register ***************/ 05846 #define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) 05848 /**************** Bit definition for USB_COUNT0_TX_1 register ***************/ 05849 #define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) 05851 /**************** Bit definition for USB_COUNT1_TX_0 register ***************/ 05852 #define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) 05854 /**************** Bit definition for USB_COUNT1_TX_1 register ***************/ 05855 #define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) 05857 /**************** Bit definition for USB_COUNT2_TX_0 register ***************/ 05858 #define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) 05860 /**************** Bit definition for USB_COUNT2_TX_1 register ***************/ 05861 #define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) 05863 /**************** Bit definition for USB_COUNT3_TX_0 register ***************/ 05864 #define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) 05866 /**************** Bit definition for USB_COUNT3_TX_1 register ***************/ 05867 #define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) 05869 /**************** Bit definition for USB_COUNT4_TX_0 register ***************/ 05870 #define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) 05872 /**************** Bit definition for USB_COUNT4_TX_1 register ***************/ 05873 #define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) 05875 /**************** Bit definition for USB_COUNT5_TX_0 register ***************/ 05876 #define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) 05878 /**************** Bit definition for USB_COUNT5_TX_1 register ***************/ 05879 #define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) 05881 /**************** Bit definition for USB_COUNT6_TX_0 register ***************/ 05882 #define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) 05884 /**************** Bit definition for USB_COUNT6_TX_1 register ***************/ 05885 #define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) 05887 /**************** Bit definition for USB_COUNT7_TX_0 register ***************/ 05888 #define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) 05890 /**************** Bit definition for USB_COUNT7_TX_1 register ***************/ 05891 #define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) 05893 /*----------------------------------------------------------------------------*/ 05894 05895 /***************** Bit definition for USB_ADDR0_RX register *****************/ 05896 #define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) 05898 /***************** Bit definition for USB_ADDR1_RX register *****************/ 05899 #define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) 05901 /***************** Bit definition for USB_ADDR2_RX register *****************/ 05902 #define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) 05904 /***************** Bit definition for USB_ADDR3_RX register *****************/ 05905 #define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) 05907 /***************** Bit definition for USB_ADDR4_RX register *****************/ 05908 #define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) 05910 /***************** Bit definition for USB_ADDR5_RX register *****************/ 05911 #define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) 05913 /***************** Bit definition for USB_ADDR6_RX register *****************/ 05914 #define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) 05916 /***************** Bit definition for USB_ADDR7_RX register *****************/ 05917 #define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) 05919 /*----------------------------------------------------------------------------*/ 05920 05921 /***************** Bit definition for USB_COUNT0_RX register ****************/ 05922 #define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) 05924 #define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) 05925 #define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) 05926 #define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) 05927 #define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) 05928 #define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) 05929 #define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) 05931 #define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) 05933 /***************** Bit definition for USB_COUNT1_RX register ****************/ 05934 #define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) 05936 #define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) 05937 #define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) 05938 #define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) 05939 #define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) 05940 #define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) 05941 #define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) 05943 #define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) 05945 /***************** Bit definition for USB_COUNT2_RX register ****************/ 05946 #define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) 05948 #define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) 05949 #define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) 05950 #define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) 05951 #define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) 05952 #define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) 05953 #define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) 05955 #define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) 05957 /***************** Bit definition for USB_COUNT3_RX register ****************/ 05958 #define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) 05960 #define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) 05961 #define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) 05962 #define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) 05963 #define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) 05964 #define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) 05965 #define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) 05967 #define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) 05969 /***************** Bit definition for USB_COUNT4_RX register ****************/ 05970 #define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) 05972 #define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) 05973 #define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) 05974 #define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) 05975 #define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) 05976 #define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) 05977 #define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) 05979 #define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) 05981 /***************** Bit definition for USB_COUNT5_RX register ****************/ 05982 #define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) 05984 #define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) 05985 #define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) 05986 #define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) 05987 #define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) 05988 #define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) 05989 #define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) 05991 #define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) 05993 /***************** Bit definition for USB_COUNT6_RX register ****************/ 05994 #define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) 05996 #define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) 05997 #define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) 05998 #define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) 05999 #define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) 06000 #define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) 06001 #define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) 06003 #define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) 06005 /***************** Bit definition for USB_COUNT7_RX register ****************/ 06006 #define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) 06008 #define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) 06009 #define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) 06010 #define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) 06011 #define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) 06012 #define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) 06013 #define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) 06015 #define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) 06017 /*----------------------------------------------------------------------------*/ 06018 06019 /**************** Bit definition for USB_COUNT0_RX_0 register ***************/ 06020 #define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) 06022 #define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) 06023 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) 06024 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) 06025 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) 06026 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) 06027 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) 06029 #define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) 06031 /**************** Bit definition for USB_COUNT0_RX_1 register ***************/ 06032 #define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) 06034 #define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) 06035 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) 06036 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) 06037 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) 06038 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) 06039 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) 06041 #define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) 06043 /**************** Bit definition for USB_COUNT1_RX_0 register ***************/ 06044 #define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) 06046 #define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) 06047 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) 06048 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) 06049 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) 06050 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) 06051 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) 06053 #define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) 06055 /**************** Bit definition for USB_COUNT1_RX_1 register ***************/ 06056 #define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) 06058 #define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) 06059 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) 06060 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) 06061 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) 06062 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) 06063 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) 06065 #define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) 06067 /**************** Bit definition for USB_COUNT2_RX_0 register ***************/ 06068 #define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) 06070 #define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) 06071 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) 06072 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) 06073 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) 06074 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) 06075 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) 06077 #define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) 06079 /**************** Bit definition for USB_COUNT2_RX_1 register ***************/ 06080 #define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) 06082 #define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) 06083 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) 06084 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) 06085 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) 06086 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) 06087 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) 06089 #define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) 06091 /**************** Bit definition for USB_COUNT3_RX_0 register ***************/ 06092 #define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) 06094 #define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) 06095 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) 06096 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) 06097 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) 06098 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) 06099 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) 06101 #define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) 06103 /**************** Bit definition for USB_COUNT3_RX_1 register ***************/ 06104 #define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) 06106 #define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) 06107 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) 06108 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) 06109 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) 06110 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) 06111 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) 06113 #define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) 06115 /**************** Bit definition for USB_COUNT4_RX_0 register ***************/ 06116 #define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) 06118 #define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) 06119 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) 06120 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) 06121 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) 06122 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) 06123 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) 06125 #define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) 06127 /**************** Bit definition for USB_COUNT4_RX_1 register ***************/ 06128 #define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) 06130 #define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) 06131 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) 06132 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) 06133 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) 06134 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) 06135 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) 06137 #define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) 06139 /**************** Bit definition for USB_COUNT5_RX_0 register ***************/ 06140 #define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) 06142 #define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) 06143 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) 06144 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) 06145 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) 06146 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) 06147 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) 06149 #define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) 06151 /**************** Bit definition for USB_COUNT5_RX_1 register ***************/ 06152 #define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) 06154 #define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) 06155 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) 06156 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) 06157 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) 06158 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) 06159 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) 06161 #define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) 06163 /*************** Bit definition for USB_COUNT6_RX_0 register ***************/ 06164 #define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) 06166 #define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) 06167 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) 06168 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) 06169 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) 06170 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) 06171 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) 06173 #define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) 06175 /**************** Bit definition for USB_COUNT6_RX_1 register ***************/ 06176 #define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) 06178 #define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) 06179 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) 06180 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) 06181 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) 06182 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) 06183 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) 06185 #define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) 06187 /*************** Bit definition for USB_COUNT7_RX_0 register ****************/ 06188 #define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) 06190 #define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) 06191 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) 06192 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) 06193 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) 06194 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) 06195 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) 06197 #define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) 06199 /*************** Bit definition for USB_COUNT7_RX_1 register ****************/ 06200 #define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) 06202 #define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) 06203 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) 06204 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) 06205 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) 06206 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) 06207 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) 06209 #define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) 06211 /******************************************************************************/ 06212 /* */ 06213 /* Controller Area Network */ 06214 /* */ 06215 /******************************************************************************/ 06216 06218 /******************* Bit definition for CAN_MCR register ********************/ 06219 #define CAN_MCR_INRQ ((uint16_t)0x0001) 06220 #define CAN_MCR_SLEEP ((uint16_t)0x0002) 06221 #define CAN_MCR_TXFP ((uint16_t)0x0004) 06222 #define CAN_MCR_RFLM ((uint16_t)0x0008) 06223 #define CAN_MCR_NART ((uint16_t)0x0010) 06224 #define CAN_MCR_AWUM ((uint16_t)0x0020) 06225 #define CAN_MCR_ABOM ((uint16_t)0x0040) 06226 #define CAN_MCR_TTCM ((uint16_t)0x0080) 06227 #define CAN_MCR_RESET ((uint16_t)0x8000) 06229 /******************* Bit definition for CAN_MSR register ********************/ 06230 #define CAN_MSR_INAK ((uint16_t)0x0001) 06231 #define CAN_MSR_SLAK ((uint16_t)0x0002) 06232 #define CAN_MSR_ERRI ((uint16_t)0x0004) 06233 #define CAN_MSR_WKUI ((uint16_t)0x0008) 06234 #define CAN_MSR_SLAKI ((uint16_t)0x0010) 06235 #define CAN_MSR_TXM ((uint16_t)0x0100) 06236 #define CAN_MSR_RXM ((uint16_t)0x0200) 06237 #define CAN_MSR_SAMP ((uint16_t)0x0400) 06238 #define CAN_MSR_RX ((uint16_t)0x0800) 06240 /******************* Bit definition for CAN_TSR register ********************/ 06241 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) 06242 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) 06243 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) 06244 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) 06245 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) 06246 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) 06247 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) 06248 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) 06249 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) 06250 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) 06251 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) 06252 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) 06253 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) 06254 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) 06255 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) 06256 #define CAN_TSR_CODE ((uint32_t)0x03000000) 06258 #define CAN_TSR_TME ((uint32_t)0x1C000000) 06259 #define CAN_TSR_TME0 ((uint32_t)0x04000000) 06260 #define CAN_TSR_TME1 ((uint32_t)0x08000000) 06261 #define CAN_TSR_TME2 ((uint32_t)0x10000000) 06263 #define CAN_TSR_LOW ((uint32_t)0xE0000000) 06264 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) 06265 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) 06266 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) 06268 /******************* Bit definition for CAN_RF0R register *******************/ 06269 #define CAN_RF0R_FMP0 ((uint8_t)0x03) 06270 #define CAN_RF0R_FULL0 ((uint8_t)0x08) 06271 #define CAN_RF0R_FOVR0 ((uint8_t)0x10) 06272 #define CAN_RF0R_RFOM0 ((uint8_t)0x20) 06274 /******************* Bit definition for CAN_RF1R register *******************/ 06275 #define CAN_RF1R_FMP1 ((uint8_t)0x03) 06276 #define CAN_RF1R_FULL1 ((uint8_t)0x08) 06277 #define CAN_RF1R_FOVR1 ((uint8_t)0x10) 06278 #define CAN_RF1R_RFOM1 ((uint8_t)0x20) 06280 /******************** Bit definition for CAN_IER register *******************/ 06281 #define CAN_IER_TMEIE ((uint32_t)0x00000001) 06282 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) 06283 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) 06284 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) 06285 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) 06286 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) 06287 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) 06288 #define CAN_IER_EWGIE ((uint32_t)0x00000100) 06289 #define CAN_IER_EPVIE ((uint32_t)0x00000200) 06290 #define CAN_IER_BOFIE ((uint32_t)0x00000400) 06291 #define CAN_IER_LECIE ((uint32_t)0x00000800) 06292 #define CAN_IER_ERRIE ((uint32_t)0x00008000) 06293 #define CAN_IER_WKUIE ((uint32_t)0x00010000) 06294 #define CAN_IER_SLKIE ((uint32_t)0x00020000) 06296 /******************** Bit definition for CAN_ESR register *******************/ 06297 #define CAN_ESR_EWGF ((uint32_t)0x00000001) 06298 #define CAN_ESR_EPVF ((uint32_t)0x00000002) 06299 #define CAN_ESR_BOFF ((uint32_t)0x00000004) 06301 #define CAN_ESR_LEC ((uint32_t)0x00000070) 06302 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) 06303 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) 06304 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) 06306 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) 06307 #define CAN_ESR_REC ((uint32_t)0xFF000000) 06309 /******************* Bit definition for CAN_BTR register ********************/ 06310 #define CAN_BTR_BRP ((uint32_t)0x000003FF) 06311 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) 06312 #define CAN_BTR_TS2 ((uint32_t)0x00700000) 06313 #define CAN_BTR_SJW ((uint32_t)0x03000000) 06314 #define CAN_BTR_LBKM ((uint32_t)0x40000000) 06315 #define CAN_BTR_SILM ((uint32_t)0x80000000) 06318 /****************** Bit definition for CAN_TI0R register ********************/ 06319 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) 06320 #define CAN_TI0R_RTR ((uint32_t)0x00000002) 06321 #define CAN_TI0R_IDE ((uint32_t)0x00000004) 06322 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) 06323 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) 06325 /****************** Bit definition for CAN_TDT0R register *******************/ 06326 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) 06327 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) 06328 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) 06330 /****************** Bit definition for CAN_TDL0R register *******************/ 06331 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) 06332 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) 06333 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) 06334 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) 06336 /****************** Bit definition for CAN_TDH0R register *******************/ 06337 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) 06338 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) 06339 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) 06340 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) 06342 /******************* Bit definition for CAN_TI1R register *******************/ 06343 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) 06344 #define CAN_TI1R_RTR ((uint32_t)0x00000002) 06345 #define CAN_TI1R_IDE ((uint32_t)0x00000004) 06346 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) 06347 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) 06349 /******************* Bit definition for CAN_TDT1R register ******************/ 06350 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) 06351 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) 06352 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) 06354 /******************* Bit definition for CAN_TDL1R register ******************/ 06355 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) 06356 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) 06357 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) 06358 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) 06360 /******************* Bit definition for CAN_TDH1R register ******************/ 06361 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) 06362 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) 06363 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) 06364 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) 06366 /******************* Bit definition for CAN_TI2R register *******************/ 06367 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) 06368 #define CAN_TI2R_RTR ((uint32_t)0x00000002) 06369 #define CAN_TI2R_IDE ((uint32_t)0x00000004) 06370 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) 06371 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) 06373 /******************* Bit definition for CAN_TDT2R register ******************/ 06374 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) 06375 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) 06376 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) 06378 /******************* Bit definition for CAN_TDL2R register ******************/ 06379 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) 06380 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) 06381 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) 06382 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) 06384 /******************* Bit definition for CAN_TDH2R register ******************/ 06385 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) 06386 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) 06387 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) 06388 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) 06390 /******************* Bit definition for CAN_RI0R register *******************/ 06391 #define CAN_RI0R_RTR ((uint32_t)0x00000002) 06392 #define CAN_RI0R_IDE ((uint32_t)0x00000004) 06393 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) 06394 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) 06396 /******************* Bit definition for CAN_RDT0R register ******************/ 06397 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) 06398 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) 06399 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) 06401 /******************* Bit definition for CAN_RDL0R register ******************/ 06402 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) 06403 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) 06404 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) 06405 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) 06407 /******************* Bit definition for CAN_RDH0R register ******************/ 06408 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) 06409 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) 06410 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) 06411 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) 06413 /******************* Bit definition for CAN_RI1R register *******************/ 06414 #define CAN_RI1R_RTR ((uint32_t)0x00000002) 06415 #define CAN_RI1R_IDE ((uint32_t)0x00000004) 06416 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) 06417 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) 06419 /******************* Bit definition for CAN_RDT1R register ******************/ 06420 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) 06421 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) 06422 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) 06424 /******************* Bit definition for CAN_RDL1R register ******************/ 06425 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) 06426 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) 06427 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) 06428 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) 06430 /******************* Bit definition for CAN_RDH1R register ******************/ 06431 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) 06432 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) 06433 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) 06434 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) 06437 /******************* Bit definition for CAN_FMR register ********************/ 06438 #define CAN_FMR_FINIT ((uint8_t)0x01) 06440 /******************* Bit definition for CAN_FM1R register *******************/ 06441 #define CAN_FM1R_FBM ((uint16_t)0x3FFF) 06442 #define CAN_FM1R_FBM0 ((uint16_t)0x0001) 06443 #define CAN_FM1R_FBM1 ((uint16_t)0x0002) 06444 #define CAN_FM1R_FBM2 ((uint16_t)0x0004) 06445 #define CAN_FM1R_FBM3 ((uint16_t)0x0008) 06446 #define CAN_FM1R_FBM4 ((uint16_t)0x0010) 06447 #define CAN_FM1R_FBM5 ((uint16_t)0x0020) 06448 #define CAN_FM1R_FBM6 ((uint16_t)0x0040) 06449 #define CAN_FM1R_FBM7 ((uint16_t)0x0080) 06450 #define CAN_FM1R_FBM8 ((uint16_t)0x0100) 06451 #define CAN_FM1R_FBM9 ((uint16_t)0x0200) 06452 #define CAN_FM1R_FBM10 ((uint16_t)0x0400) 06453 #define CAN_FM1R_FBM11 ((uint16_t)0x0800) 06454 #define CAN_FM1R_FBM12 ((uint16_t)0x1000) 06455 #define CAN_FM1R_FBM13 ((uint16_t)0x2000) 06457 /******************* Bit definition for CAN_FS1R register *******************/ 06458 #define CAN_FS1R_FSC ((uint16_t)0x3FFF) 06459 #define CAN_FS1R_FSC0 ((uint16_t)0x0001) 06460 #define CAN_FS1R_FSC1 ((uint16_t)0x0002) 06461 #define CAN_FS1R_FSC2 ((uint16_t)0x0004) 06462 #define CAN_FS1R_FSC3 ((uint16_t)0x0008) 06463 #define CAN_FS1R_FSC4 ((uint16_t)0x0010) 06464 #define CAN_FS1R_FSC5 ((uint16_t)0x0020) 06465 #define CAN_FS1R_FSC6 ((uint16_t)0x0040) 06466 #define CAN_FS1R_FSC7 ((uint16_t)0x0080) 06467 #define CAN_FS1R_FSC8 ((uint16_t)0x0100) 06468 #define CAN_FS1R_FSC9 ((uint16_t)0x0200) 06469 #define CAN_FS1R_FSC10 ((uint16_t)0x0400) 06470 #define CAN_FS1R_FSC11 ((uint16_t)0x0800) 06471 #define CAN_FS1R_FSC12 ((uint16_t)0x1000) 06472 #define CAN_FS1R_FSC13 ((uint16_t)0x2000) 06474 /****************** Bit definition for CAN_FFA1R register *******************/ 06475 #define CAN_FFA1R_FFA ((uint16_t)0x3FFF) 06476 #define CAN_FFA1R_FFA0 ((uint16_t)0x0001) 06477 #define CAN_FFA1R_FFA1 ((uint16_t)0x0002) 06478 #define CAN_FFA1R_FFA2 ((uint16_t)0x0004) 06479 #define CAN_FFA1R_FFA3 ((uint16_t)0x0008) 06480 #define CAN_FFA1R_FFA4 ((uint16_t)0x0010) 06481 #define CAN_FFA1R_FFA5 ((uint16_t)0x0020) 06482 #define CAN_FFA1R_FFA6 ((uint16_t)0x0040) 06483 #define CAN_FFA1R_FFA7 ((uint16_t)0x0080) 06484 #define CAN_FFA1R_FFA8 ((uint16_t)0x0100) 06485 #define CAN_FFA1R_FFA9 ((uint16_t)0x0200) 06486 #define CAN_FFA1R_FFA10 ((uint16_t)0x0400) 06487 #define CAN_FFA1R_FFA11 ((uint16_t)0x0800) 06488 #define CAN_FFA1R_FFA12 ((uint16_t)0x1000) 06489 #define CAN_FFA1R_FFA13 ((uint16_t)0x2000) 06491 /******************* Bit definition for CAN_FA1R register *******************/ 06492 #define CAN_FA1R_FACT ((uint16_t)0x3FFF) 06493 #define CAN_FA1R_FACT0 ((uint16_t)0x0001) 06494 #define CAN_FA1R_FACT1 ((uint16_t)0x0002) 06495 #define CAN_FA1R_FACT2 ((uint16_t)0x0004) 06496 #define CAN_FA1R_FACT3 ((uint16_t)0x0008) 06497 #define CAN_FA1R_FACT4 ((uint16_t)0x0010) 06498 #define CAN_FA1R_FACT5 ((uint16_t)0x0020) 06499 #define CAN_FA1R_FACT6 ((uint16_t)0x0040) 06500 #define CAN_FA1R_FACT7 ((uint16_t)0x0080) 06501 #define CAN_FA1R_FACT8 ((uint16_t)0x0100) 06502 #define CAN_FA1R_FACT9 ((uint16_t)0x0200) 06503 #define CAN_FA1R_FACT10 ((uint16_t)0x0400) 06504 #define CAN_FA1R_FACT11 ((uint16_t)0x0800) 06505 #define CAN_FA1R_FACT12 ((uint16_t)0x1000) 06506 #define CAN_FA1R_FACT13 ((uint16_t)0x2000) 06508 /******************* Bit definition for CAN_F0R1 register *******************/ 06509 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) 06510 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) 06511 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) 06512 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) 06513 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) 06514 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) 06515 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) 06516 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) 06517 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) 06518 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) 06519 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) 06520 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) 06521 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) 06522 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) 06523 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) 06524 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) 06525 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) 06526 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) 06527 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) 06528 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) 06529 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) 06530 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) 06531 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) 06532 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) 06533 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) 06534 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) 06535 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) 06536 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) 06537 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) 06538 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) 06539 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) 06540 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) 06542 /******************* Bit definition for CAN_F1R1 register *******************/ 06543 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) 06544 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) 06545 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) 06546 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) 06547 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) 06548 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) 06549 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) 06550 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) 06551 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) 06552 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) 06553 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) 06554 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) 06555 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) 06556 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) 06557 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) 06558 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) 06559 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) 06560 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) 06561 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) 06562 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) 06563 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) 06564 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) 06565 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) 06566 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) 06567 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) 06568 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) 06569 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) 06570 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) 06571 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) 06572 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) 06573 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) 06574 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) 06576 /******************* Bit definition for CAN_F2R1 register *******************/ 06577 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) 06578 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) 06579 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) 06580 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) 06581 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) 06582 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) 06583 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) 06584 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) 06585 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) 06586 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) 06587 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) 06588 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) 06589 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) 06590 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) 06591 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) 06592 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) 06593 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) 06594 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) 06595 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) 06596 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) 06597 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) 06598 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) 06599 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) 06600 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) 06601 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) 06602 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) 06603 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) 06604 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) 06605 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) 06606 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) 06607 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) 06608 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) 06610 /******************* Bit definition for CAN_F3R1 register *******************/ 06611 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) 06612 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) 06613 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) 06614 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) 06615 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) 06616 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) 06617 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) 06618 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) 06619 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) 06620 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) 06621 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) 06622 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) 06623 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) 06624 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) 06625 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) 06626 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) 06627 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) 06628 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) 06629 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) 06630 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) 06631 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) 06632 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) 06633 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) 06634 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) 06635 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) 06636 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) 06637 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) 06638 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) 06639 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) 06640 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) 06641 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) 06642 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) 06644 /******************* Bit definition for CAN_F4R1 register *******************/ 06645 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) 06646 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) 06647 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) 06648 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) 06649 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) 06650 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) 06651 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) 06652 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) 06653 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) 06654 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) 06655 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) 06656 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) 06657 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) 06658 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) 06659 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) 06660 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) 06661 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) 06662 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) 06663 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) 06664 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) 06665 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) 06666 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) 06667 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) 06668 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) 06669 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) 06670 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) 06671 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) 06672 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) 06673 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) 06674 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) 06675 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) 06676 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) 06678 /******************* Bit definition for CAN_F5R1 register *******************/ 06679 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) 06680 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) 06681 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) 06682 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) 06683 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) 06684 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) 06685 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) 06686 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) 06687 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) 06688 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) 06689 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) 06690 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) 06691 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) 06692 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) 06693 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) 06694 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) 06695 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) 06696 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) 06697 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) 06698 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) 06699 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) 06700 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) 06701 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) 06702 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) 06703 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) 06704 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) 06705 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) 06706 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) 06707 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) 06708 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) 06709 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) 06710 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) 06712 /******************* Bit definition for CAN_F6R1 register *******************/ 06713 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) 06714 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) 06715 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) 06716 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) 06717 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) 06718 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) 06719 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) 06720 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) 06721 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) 06722 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) 06723 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) 06724 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) 06725 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) 06726 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) 06727 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) 06728 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) 06729 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) 06730 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) 06731 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) 06732 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) 06733 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) 06734 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) 06735 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) 06736 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) 06737 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) 06738 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) 06739 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) 06740 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) 06741 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) 06742 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) 06743 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) 06744 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) 06746 /******************* Bit definition for CAN_F7R1 register *******************/ 06747 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) 06748 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) 06749 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) 06750 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) 06751 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) 06752 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) 06753 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) 06754 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) 06755 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) 06756 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) 06757 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) 06758 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) 06759 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) 06760 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) 06761 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) 06762 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) 06763 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) 06764 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) 06765 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) 06766 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) 06767 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) 06768 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) 06769 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) 06770 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) 06771 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) 06772 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) 06773 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) 06774 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) 06775 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) 06776 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) 06777 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) 06778 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) 06780 /******************* Bit definition for CAN_F8R1 register *******************/ 06781 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) 06782 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) 06783 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) 06784 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) 06785 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) 06786 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) 06787 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) 06788 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) 06789 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) 06790 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) 06791 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) 06792 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) 06793 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) 06794 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) 06795 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) 06796 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) 06797 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) 06798 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) 06799 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) 06800 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) 06801 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) 06802 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) 06803 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) 06804 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) 06805 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) 06806 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) 06807 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) 06808 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) 06809 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) 06810 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) 06811 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) 06812 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) 06814 /******************* Bit definition for CAN_F9R1 register *******************/ 06815 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) 06816 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) 06817 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) 06818 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) 06819 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) 06820 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) 06821 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) 06822 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) 06823 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) 06824 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) 06825 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) 06826 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) 06827 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) 06828 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) 06829 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) 06830 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) 06831 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) 06832 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) 06833 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) 06834 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) 06835 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) 06836 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) 06837 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) 06838 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) 06839 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) 06840 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) 06841 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) 06842 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) 06843 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) 06844 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) 06845 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) 06846 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) 06848 /******************* Bit definition for CAN_F10R1 register ******************/ 06849 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) 06850 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) 06851 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) 06852 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) 06853 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) 06854 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) 06855 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) 06856 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) 06857 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) 06858 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) 06859 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) 06860 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) 06861 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) 06862 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) 06863 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) 06864 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) 06865 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) 06866 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) 06867 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) 06868 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) 06869 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) 06870 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) 06871 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) 06872 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) 06873 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) 06874 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) 06875 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) 06876 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) 06877 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) 06878 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) 06879 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) 06880 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) 06882 /******************* Bit definition for CAN_F11R1 register ******************/ 06883 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) 06884 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) 06885 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) 06886 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) 06887 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) 06888 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) 06889 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) 06890 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) 06891 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) 06892 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) 06893 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) 06894 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) 06895 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) 06896 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) 06897 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) 06898 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) 06899 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) 06900 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) 06901 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) 06902 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) 06903 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) 06904 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) 06905 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) 06906 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) 06907 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) 06908 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) 06909 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) 06910 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) 06911 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) 06912 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) 06913 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) 06914 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) 06916 /******************* Bit definition for CAN_F12R1 register ******************/ 06917 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) 06918 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) 06919 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) 06920 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) 06921 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) 06922 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) 06923 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) 06924 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) 06925 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) 06926 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) 06927 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) 06928 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) 06929 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) 06930 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) 06931 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) 06932 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) 06933 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) 06934 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) 06935 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) 06936 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) 06937 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) 06938 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) 06939 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) 06940 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) 06941 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) 06942 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) 06943 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) 06944 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) 06945 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) 06946 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) 06947 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) 06948 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) 06950 /******************* Bit definition for CAN_F13R1 register ******************/ 06951 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) 06952 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) 06953 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) 06954 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) 06955 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) 06956 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) 06957 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) 06958 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) 06959 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) 06960 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) 06961 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) 06962 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) 06963 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) 06964 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) 06965 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) 06966 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) 06967 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) 06968 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) 06969 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) 06970 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) 06971 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) 06972 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) 06973 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) 06974 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) 06975 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) 06976 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) 06977 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) 06978 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) 06979 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) 06980 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) 06981 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) 06982 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) 06984 /******************* Bit definition for CAN_F0R2 register *******************/ 06985 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) 06986 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) 06987 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) 06988 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) 06989 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) 06990 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) 06991 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) 06992 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) 06993 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) 06994 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) 06995 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) 06996 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) 06997 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) 06998 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) 06999 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) 07000 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) 07001 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) 07002 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) 07003 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) 07004 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) 07005 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) 07006 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) 07007 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) 07008 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) 07009 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) 07010 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) 07011 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) 07012 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) 07013 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) 07014 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) 07015 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) 07016 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) 07018 /******************* Bit definition for CAN_F1R2 register *******************/ 07019 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) 07020 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) 07021 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) 07022 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) 07023 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) 07024 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) 07025 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) 07026 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) 07027 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) 07028 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) 07029 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) 07030 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) 07031 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) 07032 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) 07033 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) 07034 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) 07035 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) 07036 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) 07037 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) 07038 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) 07039 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) 07040 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) 07041 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) 07042 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) 07043 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) 07044 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) 07045 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) 07046 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) 07047 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) 07048 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) 07049 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) 07050 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) 07052 /******************* Bit definition for CAN_F2R2 register *******************/ 07053 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) 07054 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) 07055 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) 07056 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) 07057 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) 07058 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) 07059 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) 07060 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) 07061 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) 07062 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) 07063 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) 07064 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) 07065 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) 07066 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) 07067 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) 07068 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) 07069 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) 07070 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) 07071 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) 07072 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) 07073 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) 07074 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) 07075 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) 07076 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) 07077 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) 07078 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) 07079 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) 07080 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) 07081 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) 07082 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) 07083 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) 07084 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) 07086 /******************* Bit definition for CAN_F3R2 register *******************/ 07087 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) 07088 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) 07089 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) 07090 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) 07091 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) 07092 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) 07093 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) 07094 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) 07095 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) 07096 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) 07097 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) 07098 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) 07099 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) 07100 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) 07101 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) 07102 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) 07103 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) 07104 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) 07105 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) 07106 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) 07107 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) 07108 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) 07109 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) 07110 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) 07111 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) 07112 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) 07113 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) 07114 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) 07115 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) 07116 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) 07117 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) 07118 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) 07120 /******************* Bit definition for CAN_F4R2 register *******************/ 07121 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) 07122 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) 07123 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) 07124 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) 07125 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) 07126 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) 07127 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) 07128 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) 07129 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) 07130 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) 07131 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) 07132 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) 07133 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) 07134 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) 07135 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) 07136 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) 07137 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) 07138 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) 07139 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) 07140 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) 07141 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) 07142 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) 07143 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) 07144 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) 07145 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) 07146 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) 07147 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) 07148 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) 07149 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) 07150 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) 07151 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) 07152 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) 07154 /******************* Bit definition for CAN_F5R2 register *******************/ 07155 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) 07156 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) 07157 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) 07158 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) 07159 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) 07160 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) 07161 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) 07162 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) 07163 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) 07164 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) 07165 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) 07166 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) 07167 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) 07168 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) 07169 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) 07170 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) 07171 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) 07172 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) 07173 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) 07174 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) 07175 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) 07176 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) 07177 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) 07178 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) 07179 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) 07180 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) 07181 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) 07182 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) 07183 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) 07184 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) 07185 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) 07186 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) 07188 /******************* Bit definition for CAN_F6R2 register *******************/ 07189 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) 07190 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) 07191 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) 07192 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) 07193 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) 07194 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) 07195 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) 07196 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) 07197 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) 07198 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) 07199 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) 07200 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) 07201 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) 07202 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) 07203 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) 07204 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) 07205 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) 07206 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) 07207 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) 07208 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) 07209 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) 07210 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) 07211 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) 07212 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) 07213 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) 07214 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) 07215 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) 07216 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) 07217 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) 07218 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) 07219 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) 07220 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) 07222 /******************* Bit definition for CAN_F7R2 register *******************/ 07223 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) 07224 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) 07225 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) 07226 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) 07227 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) 07228 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) 07229 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) 07230 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) 07231 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) 07232 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) 07233 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) 07234 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) 07235 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) 07236 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) 07237 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) 07238 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) 07239 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) 07240 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) 07241 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) 07242 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) 07243 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) 07244 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) 07245 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) 07246 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) 07247 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) 07248 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) 07249 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) 07250 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) 07251 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) 07252 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) 07253 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) 07254 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) 07256 /******************* Bit definition for CAN_F8R2 register *******************/ 07257 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) 07258 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) 07259 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) 07260 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) 07261 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) 07262 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) 07263 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) 07264 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) 07265 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) 07266 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) 07267 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) 07268 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) 07269 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) 07270 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) 07271 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) 07272 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) 07273 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) 07274 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) 07275 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) 07276 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) 07277 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) 07278 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) 07279 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) 07280 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) 07281 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) 07282 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) 07283 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) 07284 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) 07285 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) 07286 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) 07287 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) 07288 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) 07290 /******************* Bit definition for CAN_F9R2 register *******************/ 07291 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) 07292 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) 07293 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) 07294 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) 07295 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) 07296 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) 07297 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) 07298 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) 07299 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) 07300 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) 07301 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) 07302 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) 07303 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) 07304 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) 07305 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) 07306 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) 07307 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) 07308 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) 07309 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) 07310 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) 07311 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) 07312 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) 07313 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) 07314 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) 07315 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) 07316 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) 07317 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) 07318 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) 07319 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) 07320 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) 07321 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) 07322 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) 07324 /******************* Bit definition for CAN_F10R2 register ******************/ 07325 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) 07326 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) 07327 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) 07328 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) 07329 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) 07330 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) 07331 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) 07332 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) 07333 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) 07334 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) 07335 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) 07336 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) 07337 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) 07338 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) 07339 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) 07340 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) 07341 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) 07342 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) 07343 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) 07344 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) 07345 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) 07346 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) 07347 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) 07348 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) 07349 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) 07350 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) 07351 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) 07352 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) 07353 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) 07354 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) 07355 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) 07356 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) 07358 /******************* Bit definition for CAN_F11R2 register ******************/ 07359 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) 07360 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) 07361 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) 07362 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) 07363 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) 07364 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) 07365 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) 07366 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) 07367 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) 07368 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) 07369 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) 07370 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) 07371 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) 07372 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) 07373 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) 07374 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) 07375 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) 07376 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) 07377 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) 07378 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) 07379 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) 07380 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) 07381 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) 07382 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) 07383 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) 07384 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) 07385 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) 07386 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) 07387 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) 07388 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) 07389 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) 07390 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) 07392 /******************* Bit definition for CAN_F12R2 register ******************/ 07393 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) 07394 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) 07395 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) 07396 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) 07397 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) 07398 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) 07399 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) 07400 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) 07401 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) 07402 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) 07403 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) 07404 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) 07405 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) 07406 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) 07407 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) 07408 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) 07409 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) 07410 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) 07411 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) 07412 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) 07413 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) 07414 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) 07415 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) 07416 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) 07417 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) 07418 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) 07419 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) 07420 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) 07421 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) 07422 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) 07423 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) 07424 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) 07426 /******************* Bit definition for CAN_F13R2 register ******************/ 07427 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) 07428 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) 07429 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) 07430 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) 07431 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) 07432 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) 07433 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) 07434 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) 07435 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) 07436 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) 07437 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) 07438 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) 07439 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) 07440 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) 07441 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) 07442 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) 07443 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) 07444 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) 07445 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) 07446 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) 07447 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) 07448 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) 07449 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) 07450 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) 07451 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) 07452 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) 07453 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) 07454 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) 07455 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) 07456 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) 07457 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) 07458 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) 07460 /******************************************************************************/ 07461 /* */ 07462 /* Serial Peripheral Interface */ 07463 /* */ 07464 /******************************************************************************/ 07465 07466 /******************* Bit definition for SPI_CR1 register ********************/ 07467 #define SPI_CR1_CPHA ((uint16_t)0x0001) 07468 #define SPI_CR1_CPOL ((uint16_t)0x0002) 07469 #define SPI_CR1_MSTR ((uint16_t)0x0004) 07471 #define SPI_CR1_BR ((uint16_t)0x0038) 07472 #define SPI_CR1_BR_0 ((uint16_t)0x0008) 07473 #define SPI_CR1_BR_1 ((uint16_t)0x0010) 07474 #define SPI_CR1_BR_2 ((uint16_t)0x0020) 07476 #define SPI_CR1_SPE ((uint16_t)0x0040) 07477 #define SPI_CR1_LSBFIRST ((uint16_t)0x0080) 07478 #define SPI_CR1_SSI ((uint16_t)0x0100) 07479 #define SPI_CR1_SSM ((uint16_t)0x0200) 07480 #define SPI_CR1_RXONLY ((uint16_t)0x0400) 07481 #define SPI_CR1_DFF ((uint16_t)0x0800) 07482 #define SPI_CR1_CRCNEXT ((uint16_t)0x1000) 07483 #define SPI_CR1_CRCEN ((uint16_t)0x2000) 07484 #define SPI_CR1_BIDIOE ((uint16_t)0x4000) 07485 #define SPI_CR1_BIDIMODE ((uint16_t)0x8000) 07487 /******************* Bit definition for SPI_CR2 register ********************/ 07488 #define SPI_CR2_RXDMAEN ((uint8_t)0x01) 07489 #define SPI_CR2_TXDMAEN ((uint8_t)0x02) 07490 #define SPI_CR2_SSOE ((uint8_t)0x04) 07491 #define SPI_CR2_ERRIE ((uint8_t)0x20) 07492 #define SPI_CR2_RXNEIE ((uint8_t)0x40) 07493 #define SPI_CR2_TXEIE ((uint8_t)0x80) 07495 /******************** Bit definition for SPI_SR register ********************/ 07496 #define SPI_SR_RXNE ((uint8_t)0x01) 07497 #define SPI_SR_TXE ((uint8_t)0x02) 07498 #define SPI_SR_CHSIDE ((uint8_t)0x04) 07499 #define SPI_SR_UDR ((uint8_t)0x08) 07500 #define SPI_SR_CRCERR ((uint8_t)0x10) 07501 #define SPI_SR_MODF ((uint8_t)0x20) 07502 #define SPI_SR_OVR ((uint8_t)0x40) 07503 #define SPI_SR_BSY ((uint8_t)0x80) 07505 /******************** Bit definition for SPI_DR register ********************/ 07506 #define SPI_DR_DR ((uint16_t)0xFFFF) 07508 /******************* Bit definition for SPI_CRCPR register ******************/ 07509 #define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) 07511 /****************** Bit definition for SPI_RXCRCR register ******************/ 07512 #define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) 07514 /****************** Bit definition for SPI_TXCRCR register ******************/ 07515 #define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) 07517 /****************** Bit definition for SPI_I2SCFGR register *****************/ 07518 #define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) 07520 #define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) 07521 #define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) 07522 #define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) 07524 #define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) 07526 #define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) 07527 #define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) 07528 #define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) 07530 #define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) 07532 #define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) 07533 #define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) 07534 #define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) 07536 #define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) 07537 #define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) 07539 /****************** Bit definition for SPI_I2SPR register *******************/ 07540 #define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) 07541 #define SPI_I2SPR_ODD ((uint16_t)0x0100) 07542 #define SPI_I2SPR_MCKOE ((uint16_t)0x0200) 07544 /******************************************************************************/ 07545 /* */ 07546 /* Inter-integrated Circuit Interface */ 07547 /* */ 07548 /******************************************************************************/ 07549 07550 /******************* Bit definition for I2C_CR1 register ********************/ 07551 #define I2C_CR1_PE ((uint16_t)0x0001) 07552 #define I2C_CR1_SMBUS ((uint16_t)0x0002) 07553 #define I2C_CR1_SMBTYPE ((uint16_t)0x0008) 07554 #define I2C_CR1_ENARP ((uint16_t)0x0010) 07555 #define I2C_CR1_ENPEC ((uint16_t)0x0020) 07556 #define I2C_CR1_ENGC ((uint16_t)0x0040) 07557 #define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) 07558 #define I2C_CR1_START ((uint16_t)0x0100) 07559 #define I2C_CR1_STOP ((uint16_t)0x0200) 07560 #define I2C_CR1_ACK ((uint16_t)0x0400) 07561 #define I2C_CR1_POS ((uint16_t)0x0800) 07562 #define I2C_CR1_PEC ((uint16_t)0x1000) 07563 #define I2C_CR1_ALERT ((uint16_t)0x2000) 07564 #define I2C_CR1_SWRST ((uint16_t)0x8000) 07566 /******************* Bit definition for I2C_CR2 register ********************/ 07567 #define I2C_CR2_FREQ ((uint16_t)0x003F) 07568 #define I2C_CR2_FREQ_0 ((uint16_t)0x0001) 07569 #define I2C_CR2_FREQ_1 ((uint16_t)0x0002) 07570 #define I2C_CR2_FREQ_2 ((uint16_t)0x0004) 07571 #define I2C_CR2_FREQ_3 ((uint16_t)0x0008) 07572 #define I2C_CR2_FREQ_4 ((uint16_t)0x0010) 07573 #define I2C_CR2_FREQ_5 ((uint16_t)0x0020) 07575 #define I2C_CR2_ITERREN ((uint16_t)0x0100) 07576 #define I2C_CR2_ITEVTEN ((uint16_t)0x0200) 07577 #define I2C_CR2_ITBUFEN ((uint16_t)0x0400) 07578 #define I2C_CR2_DMAEN ((uint16_t)0x0800) 07579 #define I2C_CR2_LAST ((uint16_t)0x1000) 07581 /******************* Bit definition for I2C_OAR1 register *******************/ 07582 #define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) 07583 #define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) 07585 #define I2C_OAR1_ADD0 ((uint16_t)0x0001) 07586 #define I2C_OAR1_ADD1 ((uint16_t)0x0002) 07587 #define I2C_OAR1_ADD2 ((uint16_t)0x0004) 07588 #define I2C_OAR1_ADD3 ((uint16_t)0x0008) 07589 #define I2C_OAR1_ADD4 ((uint16_t)0x0010) 07590 #define I2C_OAR1_ADD5 ((uint16_t)0x0020) 07591 #define I2C_OAR1_ADD6 ((uint16_t)0x0040) 07592 #define I2C_OAR1_ADD7 ((uint16_t)0x0080) 07593 #define I2C_OAR1_ADD8 ((uint16_t)0x0100) 07594 #define I2C_OAR1_ADD9 ((uint16_t)0x0200) 07596 #define I2C_OAR1_ADDMODE ((uint16_t)0x8000) 07598 /******************* Bit definition for I2C_OAR2 register *******************/ 07599 #define I2C_OAR2_ENDUAL ((uint8_t)0x01) 07600 #define I2C_OAR2_ADD2 ((uint8_t)0xFE) 07602 /******************** Bit definition for I2C_DR register ********************/ 07603 #define I2C_DR_DR ((uint8_t)0xFF) 07605 /******************* Bit definition for I2C_SR1 register ********************/ 07606 #define I2C_SR1_SB ((uint16_t)0x0001) 07607 #define I2C_SR1_ADDR ((uint16_t)0x0002) 07608 #define I2C_SR1_BTF ((uint16_t)0x0004) 07609 #define I2C_SR1_ADD10 ((uint16_t)0x0008) 07610 #define I2C_SR1_STOPF ((uint16_t)0x0010) 07611 #define I2C_SR1_RXNE ((uint16_t)0x0040) 07612 #define I2C_SR1_TXE ((uint16_t)0x0080) 07613 #define I2C_SR1_BERR ((uint16_t)0x0100) 07614 #define I2C_SR1_ARLO ((uint16_t)0x0200) 07615 #define I2C_SR1_AF ((uint16_t)0x0400) 07616 #define I2C_SR1_OVR ((uint16_t)0x0800) 07617 #define I2C_SR1_PECERR ((uint16_t)0x1000) 07618 #define I2C_SR1_TIMEOUT ((uint16_t)0x4000) 07619 #define I2C_SR1_SMBALERT ((uint16_t)0x8000) 07621 /******************* Bit definition for I2C_SR2 register ********************/ 07622 #define I2C_SR2_MSL ((uint16_t)0x0001) 07623 #define I2C_SR2_BUSY ((uint16_t)0x0002) 07624 #define I2C_SR2_TRA ((uint16_t)0x0004) 07625 #define I2C_SR2_GENCALL ((uint16_t)0x0010) 07626 #define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) 07627 #define I2C_SR2_SMBHOST ((uint16_t)0x0040) 07628 #define I2C_SR2_DUALF ((uint16_t)0x0080) 07629 #define I2C_SR2_PEC ((uint16_t)0xFF00) 07631 /******************* Bit definition for I2C_CCR register ********************/ 07632 #define I2C_CCR_CCR ((uint16_t)0x0FFF) 07633 #define I2C_CCR_DUTY ((uint16_t)0x4000) 07634 #define I2C_CCR_FS ((uint16_t)0x8000) 07636 /****************** Bit definition for I2C_TRISE register *******************/ 07637 #define I2C_TRISE_TRISE ((uint8_t)0x3F) 07639 /******************************************************************************/ 07640 /* */ 07641 /* Universal Synchronous Asynchronous Receiver Transmitter */ 07642 /* */ 07643 /******************************************************************************/ 07644 07645 /******************* Bit definition for USART_SR register *******************/ 07646 #define USART_SR_PE ((uint16_t)0x0001) 07647 #define USART_SR_FE ((uint16_t)0x0002) 07648 #define USART_SR_NE ((uint16_t)0x0004) 07649 #define USART_SR_ORE ((uint16_t)0x0008) 07650 #define USART_SR_IDLE ((uint16_t)0x0010) 07651 #define USART_SR_RXNE ((uint16_t)0x0020) 07652 #define USART_SR_TC ((uint16_t)0x0040) 07653 #define USART_SR_TXE ((uint16_t)0x0080) 07654 #define USART_SR_LBD ((uint16_t)0x0100) 07655 #define USART_SR_CTS ((uint16_t)0x0200) 07657 /******************* Bit definition for USART_DR register *******************/ 07658 #define USART_DR_DR ((uint16_t)0x01FF) 07660 /****************** Bit definition for USART_BRR register *******************/ 07661 #define USART_BRR_DIV_Fraction ((uint16_t)0x000F) 07662 #define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) 07664 /****************** Bit definition for USART_CR1 register *******************/ 07665 #define USART_CR1_SBK ((uint16_t)0x0001) 07666 #define USART_CR1_RWU ((uint16_t)0x0002) 07667 #define USART_CR1_RE ((uint16_t)0x0004) 07668 #define USART_CR1_TE ((uint16_t)0x0008) 07669 #define USART_CR1_IDLEIE ((uint16_t)0x0010) 07670 #define USART_CR1_RXNEIE ((uint16_t)0x0020) 07671 #define USART_CR1_TCIE ((uint16_t)0x0040) 07672 #define USART_CR1_TXEIE ((uint16_t)0x0080) 07673 #define USART_CR1_PEIE ((uint16_t)0x0100) 07674 #define USART_CR1_PS ((uint16_t)0x0200) 07675 #define USART_CR1_PCE ((uint16_t)0x0400) 07676 #define USART_CR1_WAKE ((uint16_t)0x0800) 07677 #define USART_CR1_M ((uint16_t)0x1000) 07678 #define USART_CR1_UE ((uint16_t)0x2000) 07679 #define USART_CR1_OVER8 ((uint16_t)0x8000) 07681 /****************** Bit definition for USART_CR2 register *******************/ 07682 #define USART_CR2_ADD ((uint16_t)0x000F) 07683 #define USART_CR2_LBDL ((uint16_t)0x0020) 07684 #define USART_CR2_LBDIE ((uint16_t)0x0040) 07685 #define USART_CR2_LBCL ((uint16_t)0x0100) 07686 #define USART_CR2_CPHA ((uint16_t)0x0200) 07687 #define USART_CR2_CPOL ((uint16_t)0x0400) 07688 #define USART_CR2_CLKEN ((uint16_t)0x0800) 07690 #define USART_CR2_STOP ((uint16_t)0x3000) 07691 #define USART_CR2_STOP_0 ((uint16_t)0x1000) 07692 #define USART_CR2_STOP_1 ((uint16_t)0x2000) 07694 #define USART_CR2_LINEN ((uint16_t)0x4000) 07696 /****************** Bit definition for USART_CR3 register *******************/ 07697 #define USART_CR3_EIE ((uint16_t)0x0001) 07698 #define USART_CR3_IREN ((uint16_t)0x0002) 07699 #define USART_CR3_IRLP ((uint16_t)0x0004) 07700 #define USART_CR3_HDSEL ((uint16_t)0x0008) 07701 #define USART_CR3_NACK ((uint16_t)0x0010) 07702 #define USART_CR3_SCEN ((uint16_t)0x0020) 07703 #define USART_CR3_DMAR ((uint16_t)0x0040) 07704 #define USART_CR3_DMAT ((uint16_t)0x0080) 07705 #define USART_CR3_RTSE ((uint16_t)0x0100) 07706 #define USART_CR3_CTSE ((uint16_t)0x0200) 07707 #define USART_CR3_CTSIE ((uint16_t)0x0400) 07708 #define USART_CR3_ONEBIT ((uint16_t)0x0800) 07710 /****************** Bit definition for USART_GTPR register ******************/ 07711 #define USART_GTPR_PSC ((uint16_t)0x00FF) 07712 #define USART_GTPR_PSC_0 ((uint16_t)0x0001) 07713 #define USART_GTPR_PSC_1 ((uint16_t)0x0002) 07714 #define USART_GTPR_PSC_2 ((uint16_t)0x0004) 07715 #define USART_GTPR_PSC_3 ((uint16_t)0x0008) 07716 #define USART_GTPR_PSC_4 ((uint16_t)0x0010) 07717 #define USART_GTPR_PSC_5 ((uint16_t)0x0020) 07718 #define USART_GTPR_PSC_6 ((uint16_t)0x0040) 07719 #define USART_GTPR_PSC_7 ((uint16_t)0x0080) 07721 #define USART_GTPR_GT ((uint16_t)0xFF00) 07723 /******************************************************************************/ 07724 /* */ 07725 /* Debug MCU */ 07726 /* */ 07727 /******************************************************************************/ 07728 07729 /**************** Bit definition for DBGMCU_IDCODE register *****************/ 07730 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) 07732 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) 07733 #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) 07734 #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) 07735 #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) 07736 #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) 07737 #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) 07738 #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) 07739 #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) 07740 #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) 07741 #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) 07742 #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) 07743 #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) 07744 #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) 07745 #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) 07746 #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) 07747 #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) 07748 #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) 07750 /****************** Bit definition for DBGMCU_CR register *******************/ 07751 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) 07752 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) 07753 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) 07754 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) 07756 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) 07757 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) 07758 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) 07760 #define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) 07761 #define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) 07762 #define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) 07763 #define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) 07764 #define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) 07765 #define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) 07766 #define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) 07767 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) 07768 #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) 07769 #define DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) 07770 #define DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) 07771 #define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) 07772 #define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) 07773 #define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) 07774 #define DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) 07775 #define DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) 07776 #define DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) 07777 #define DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) 07778 #define DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) 07779 #define DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) 07780 #define DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) 07781 #define DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) 07782 #define DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) 07784 /******************************************************************************/ 07785 /* */ 07786 /* FLASH and Option Bytes Registers */ 07787 /* */ 07788 /******************************************************************************/ 07789 07790 /******************* Bit definition for FLASH_ACR register ******************/ 07791 #define FLASH_ACR_LATENCY ((uint8_t)0x03) 07792 #define FLASH_ACR_LATENCY_0 ((uint8_t)0x00) 07793 #define FLASH_ACR_LATENCY_1 ((uint8_t)0x01) 07794 #define FLASH_ACR_LATENCY_2 ((uint8_t)0x02) 07796 #define FLASH_ACR_HLFCYA ((uint8_t)0x08) 07797 #define FLASH_ACR_PRFTBE ((uint8_t)0x10) 07798 #define FLASH_ACR_PRFTBS ((uint8_t)0x20) 07800 /****************** Bit definition for FLASH_KEYR register ******************/ 07801 #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) 07803 /***************** Bit definition for FLASH_OPTKEYR register ****************/ 07804 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) 07806 /****************** Bit definition for FLASH_SR register *******************/ 07807 #define FLASH_SR_BSY ((uint8_t)0x01) 07808 #define FLASH_SR_PGERR ((uint8_t)0x04) 07809 #define FLASH_SR_WRPRTERR ((uint8_t)0x10) 07810 #define FLASH_SR_EOP ((uint8_t)0x20) 07812 /******************* Bit definition for FLASH_CR register *******************/ 07813 #define FLASH_CR_PG ((uint16_t)0x0001) 07814 #define FLASH_CR_PER ((uint16_t)0x0002) 07815 #define FLASH_CR_MER ((uint16_t)0x0004) 07816 #define FLASH_CR_OPTPG ((uint16_t)0x0010) 07817 #define FLASH_CR_OPTER ((uint16_t)0x0020) 07818 #define FLASH_CR_STRT ((uint16_t)0x0040) 07819 #define FLASH_CR_LOCK ((uint16_t)0x0080) 07820 #define FLASH_CR_OPTWRE ((uint16_t)0x0200) 07821 #define FLASH_CR_ERRIE ((uint16_t)0x0400) 07822 #define FLASH_CR_EOPIE ((uint16_t)0x1000) 07824 /******************* Bit definition for FLASH_AR register *******************/ 07825 #define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) 07827 /****************** Bit definition for FLASH_OBR register *******************/ 07828 #define FLASH_OBR_OPTERR ((uint16_t)0x0001) 07829 #define FLASH_OBR_RDPRT ((uint16_t)0x0002) 07831 #define FLASH_OBR_USER ((uint16_t)0x03FC) 07832 #define FLASH_OBR_WDG_SW ((uint16_t)0x0004) 07833 #define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) 07834 #define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) 07835 #define FLASH_OBR_BFB2 ((uint16_t)0x0020) 07837 /****************** Bit definition for FLASH_WRPR register ******************/ 07838 #define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) 07840 /*----------------------------------------------------------------------------*/ 07841 07842 /****************** Bit definition for FLASH_RDP register *******************/ 07843 #define FLASH_RDP_RDP ((uint32_t)0x000000FF) 07844 #define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) 07846 /****************** Bit definition for FLASH_USER register ******************/ 07847 #define FLASH_USER_USER ((uint32_t)0x00FF0000) 07848 #define FLASH_USER_nUSER ((uint32_t)0xFF000000) 07850 /****************** Bit definition for FLASH_Data0 register *****************/ 07851 #define FLASH_Data0_Data0 ((uint32_t)0x000000FF) 07852 #define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) 07854 /****************** Bit definition for FLASH_Data1 register *****************/ 07855 #define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) 07856 #define FLASH_Data1_nData1 ((uint32_t)0xFF000000) 07858 /****************** Bit definition for FLASH_WRP0 register ******************/ 07859 #define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) 07860 #define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) 07862 /****************** Bit definition for FLASH_WRP1 register ******************/ 07863 #define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) 07864 #define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) 07866 /****************** Bit definition for FLASH_WRP2 register ******************/ 07867 #define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) 07868 #define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) 07870 /****************** Bit definition for FLASH_WRP3 register ******************/ 07871 #define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) 07872 #define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) 07874 #ifdef STM32F10X_CL 07875 /******************************************************************************/ 07876 /* Ethernet MAC Registers bits definitions */ 07877 /******************************************************************************/ 07878 /* Bit definition for Ethernet MAC Control Register register */ 07879 #define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */ 07880 #define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */ 07881 #define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */ 07882 #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ 07883 #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ 07884 #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ 07885 #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ 07886 #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ 07887 #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ 07888 #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ 07889 #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ 07890 #define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */ 07891 #define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */ 07892 #define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */ 07893 #define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */ 07894 #define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */ 07895 #define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */ 07896 #define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */ 07897 #define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */ 07898 #define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling 07899 a transmission attempt during retries after a collision: 0 =< r <2^k */ 07900 #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */ 07901 #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */ 07902 #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */ 07903 #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */ 07904 #define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */ 07905 #define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */ 07906 #define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */ 07907 07908 /* Bit definition for Ethernet MAC Frame Filter Register */ 07909 #define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */ 07910 #define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */ 07911 #define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */ 07912 #define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */ 07913 #define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */ 07914 #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ 07915 #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ 07916 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ 07917 #define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */ 07918 #define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */ 07919 #define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */ 07920 #define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */ 07921 #define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */ 07922 #define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */ 07923 07924 /* Bit definition for Ethernet MAC Hash Table High Register */ 07925 #define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */ 07926 07927 /* Bit definition for Ethernet MAC Hash Table Low Register */ 07928 #define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */ 07929 07930 /* Bit definition for Ethernet MAC MII Address Register */ 07931 #define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */ 07932 #define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */ 07933 #define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */ 07934 #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */ 07935 #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ 07936 #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ 07937 #define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */ 07938 #define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */ 07939 07940 /* Bit definition for Ethernet MAC MII Data Register */ 07941 #define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */ 07942 07943 /* Bit definition for Ethernet MAC Flow Control Register */ 07944 #define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */ 07945 #define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */ 07946 #define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */ 07947 #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ 07948 #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */ 07949 #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */ 07950 #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ 07951 #define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */ 07952 #define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */ 07953 #define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */ 07954 #define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */ 07955 07956 /* Bit definition for Ethernet MAC VLAN Tag Register */ 07957 #define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */ 07958 #define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ 07959 07960 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ 07961 #define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */ 07962 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. 07963 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ 07964 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask 07965 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask 07966 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask 07967 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask 07968 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - 07969 RSVD - Filter1 Command - RSVD - Filter0 Command 07970 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset 07971 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 07972 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ 07973 07974 /* Bit definition for Ethernet MAC PMT Control and Status Register */ 07975 #define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ 07976 #define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */ 07977 #define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */ 07978 #define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */ 07979 #define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */ 07980 #define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */ 07981 #define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */ 07982 07983 /* Bit definition for Ethernet MAC Status Register */ 07984 #define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */ 07985 #define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */ 07986 #define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */ 07987 #define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */ 07988 #define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */ 07989 07990 /* Bit definition for Ethernet MAC Interrupt Mask Register */ 07991 #define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */ 07992 #define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */ 07993 07994 /* Bit definition for Ethernet MAC Address0 High Register */ 07995 #define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */ 07996 07997 /* Bit definition for Ethernet MAC Address0 Low Register */ 07998 #define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */ 07999 08000 /* Bit definition for Ethernet MAC Address1 High Register */ 08001 #define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */ 08002 #define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */ 08003 #define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ 08004 #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ 08005 #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ 08006 #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ 08007 #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ 08008 #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ 08009 #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ 08010 #define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */ 08011 08012 /* Bit definition for Ethernet MAC Address1 Low Register */ 08013 #define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */ 08014 08015 /* Bit definition for Ethernet MAC Address2 High Register */ 08016 #define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */ 08017 #define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */ 08018 #define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ 08019 #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ 08020 #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ 08021 #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ 08022 #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ 08023 #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ 08024 #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ 08025 #define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */ 08026 08027 /* Bit definition for Ethernet MAC Address2 Low Register */ 08028 #define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */ 08029 08030 /* Bit definition for Ethernet MAC Address3 High Register */ 08031 #define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */ 08032 #define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */ 08033 #define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ 08034 #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ 08035 #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ 08036 #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ 08037 #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ 08038 #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ 08039 #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ 08040 #define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */ 08041 08042 /* Bit definition for Ethernet MAC Address3 Low Register */ 08043 #define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */ 08044 08045 /******************************************************************************/ 08046 /* Ethernet MMC Registers bits definition */ 08047 /******************************************************************************/ 08048 08049 /* Bit definition for Ethernet MMC Contol Register */ 08050 #define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */ 08051 #define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */ 08052 #define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */ 08053 #define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */ 08054 08055 /* Bit definition for Ethernet MMC Receive Interrupt Register */ 08056 #define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ 08057 #define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ 08058 #define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ 08059 08060 /* Bit definition for Ethernet MMC Transmit Interrupt Register */ 08061 #define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ 08062 #define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ 08063 #define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ 08064 08065 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */ 08066 #define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ 08067 #define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ 08068 #define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ 08069 08070 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */ 08071 #define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ 08072 #define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ 08073 #define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ 08074 08075 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */ 08076 #define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ 08077 08078 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */ 08079 #define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ 08080 08081 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */ 08082 #define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */ 08083 08084 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */ 08085 #define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */ 08086 08087 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */ 08088 #define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ 08089 08090 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */ 08091 #define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */ 08092 08093 /******************************************************************************/ 08094 /* Ethernet PTP Registers bits definition */ 08095 /******************************************************************************/ 08096 08097 /* Bit definition for Ethernet PTP Time Stamp Contol Register */ 08098 #define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */ 08099 #define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */ 08100 #define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */ 08101 #define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */ 08102 #define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */ 08103 #define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */ 08104 08105 /* Bit definition for Ethernet PTP Sub-Second Increment Register */ 08106 #define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */ 08107 08108 /* Bit definition for Ethernet PTP Time Stamp High Register */ 08109 #define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */ 08110 08111 /* Bit definition for Ethernet PTP Time Stamp Low Register */ 08112 #define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */ 08113 #define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */ 08114 08115 /* Bit definition for Ethernet PTP Time Stamp High Update Register */ 08116 #define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */ 08117 08118 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */ 08119 #define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */ 08120 #define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */ 08121 08122 /* Bit definition for Ethernet PTP Time Stamp Addend Register */ 08123 #define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */ 08124 08125 /* Bit definition for Ethernet PTP Target Time High Register */ 08126 #define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */ 08127 08128 /* Bit definition for Ethernet PTP Target Time Low Register */ 08129 #define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */ 08130 08131 /******************************************************************************/ 08132 /* Ethernet DMA Registers bits definition */ 08133 /******************************************************************************/ 08134 08135 /* Bit definition for Ethernet DMA Bus Mode Register */ 08136 #define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */ 08137 #define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */ 08138 #define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */ 08139 #define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */ 08140 #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ 08141 #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ 08142 #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ 08143 #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ 08144 #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ 08145 #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ 08146 #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ 08147 #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ 08148 #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ 08149 #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ 08150 #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ 08151 #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ 08152 #define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */ 08153 #define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ 08154 #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */ 08155 #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */ 08156 #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */ 08157 #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ 08158 #define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */ 08159 #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ 08160 #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ 08161 #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ 08162 #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ 08163 #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ 08164 #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ 08165 #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ 08166 #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ 08167 #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ 08168 #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ 08169 #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ 08170 #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ 08171 #define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */ 08172 #define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */ 08173 #define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */ 08174 08175 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */ 08176 #define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */ 08177 08178 /* Bit definition for Ethernet DMA Receive Poll Demand Register */ 08179 #define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */ 08180 08181 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */ 08182 #define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */ 08183 08184 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */ 08185 #define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */ 08186 08187 /* Bit definition for Ethernet DMA Status Register */ 08188 #define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */ 08189 #define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */ 08190 #define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */ 08191 #define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */ 08192 /* combination with EBS[2:0] for GetFlagStatus function */ 08193 #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ 08194 #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ 08195 #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ 08196 #define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */ 08197 #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ 08198 #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */ 08199 #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */ 08200 #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */ 08201 #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */ 08202 #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */ 08203 #define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */ 08204 #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ 08205 #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */ 08206 #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */ 08207 #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */ 08208 #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */ 08209 #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */ 08210 #define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */ 08211 #define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */ 08212 #define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */ 08213 #define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */ 08214 #define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */ 08215 #define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */ 08216 #define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */ 08217 #define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */ 08218 #define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */ 08219 #define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */ 08220 #define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */ 08221 #define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */ 08222 #define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */ 08223 #define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */ 08224 #define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */ 08225 08226 /* Bit definition for Ethernet DMA Operation Mode Register */ 08227 #define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ 08228 #define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */ 08229 #define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */ 08230 #define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */ 08231 #define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */ 08232 #define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */ 08233 #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ 08234 #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ 08235 #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ 08236 #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ 08237 #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ 08238 #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ 08239 #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ 08240 #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ 08241 #define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */ 08242 #define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */ 08243 #define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */ 08244 #define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */ 08245 #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ 08246 #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ 08247 #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ 08248 #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ 08249 #define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */ 08250 #define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */ 08251 08252 /* Bit definition for Ethernet DMA Interrupt Enable Register */ 08253 #define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */ 08254 #define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */ 08255 #define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */ 08256 #define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */ 08257 #define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */ 08258 #define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */ 08259 #define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */ 08260 #define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */ 08261 #define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */ 08262 #define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */ 08263 #define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */ 08264 #define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */ 08265 #define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */ 08266 #define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */ 08267 #define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */ 08268 08269 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */ 08270 #define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ 08271 #define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */ 08272 #define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */ 08273 #define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */ 08274 08275 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */ 08276 #define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */ 08277 08278 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */ 08279 #define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */ 08280 08281 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */ 08282 #define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */ 08283 08284 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */ 08285 #define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */ 08286 #endif /* STM32F10X_CL */ 08287 08296 #ifdef USE_STDPERIPH_DRIVER 08297 #include "stm32f10x_conf.h" 08298 #endif 08299 08304 #define SET_BIT(REG, BIT) ((REG) |= (BIT)) 08305 08306 #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) 08307 08308 #define READ_BIT(REG, BIT) ((REG) & (BIT)) 08309 08310 #define CLEAR_REG(REG) ((REG) = (0x0)) 08311 08312 #define WRITE_REG(REG, VAL) ((REG) = (VAL)) 08313 08314 #define READ_REG(REG) ((REG)) 08315 08316 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) 08317 08322 #ifdef __cplusplus 08323 } 08324 #endif 08325 08326 #endif /* __STM32F10x_H */ 08327 08336 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
1.7.5 
