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STM32F10x Standard Peripherals Library
3.5.0
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STM32F10x Standard Peripherals Library
3.5.0
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Defines | |
| #define | FLASH_BASE ((uint32_t)0x08000000) |
| #define | SRAM_BASE ((uint32_t)0x20000000) |
| #define | PERIPH_BASE ((uint32_t)0x40000000) |
| #define | SRAM_BB_BASE ((uint32_t)0x22000000) |
| #define | PERIPH_BB_BASE ((uint32_t)0x42000000) |
| #define | FSMC_R_BASE ((uint32_t)0xA0000000) |
| #define | APB1PERIPH_BASE PERIPH_BASE |
| #define | APB2PERIPH_BASE (PERIPH_BASE + 0x10000) |
| #define | AHBPERIPH_BASE (PERIPH_BASE + 0x20000) |
| #define | TIM2_BASE (APB1PERIPH_BASE + 0x0000) |
| #define | TIM3_BASE (APB1PERIPH_BASE + 0x0400) |
| #define | TIM4_BASE (APB1PERIPH_BASE + 0x0800) |
| #define | TIM5_BASE (APB1PERIPH_BASE + 0x0C00) |
| #define | TIM6_BASE (APB1PERIPH_BASE + 0x1000) |
| #define | TIM7_BASE (APB1PERIPH_BASE + 0x1400) |
| #define | TIM12_BASE (APB1PERIPH_BASE + 0x1800) |
| #define | TIM13_BASE (APB1PERIPH_BASE + 0x1C00) |
| #define | TIM14_BASE (APB1PERIPH_BASE + 0x2000) |
| #define | RTC_BASE (APB1PERIPH_BASE + 0x2800) |
| #define | WWDG_BASE (APB1PERIPH_BASE + 0x2C00) |
| #define | IWDG_BASE (APB1PERIPH_BASE + 0x3000) |
| #define | SPI2_BASE (APB1PERIPH_BASE + 0x3800) |
| #define | SPI3_BASE (APB1PERIPH_BASE + 0x3C00) |
| #define | USART2_BASE (APB1PERIPH_BASE + 0x4400) |
| #define | USART3_BASE (APB1PERIPH_BASE + 0x4800) |
| #define | UART4_BASE (APB1PERIPH_BASE + 0x4C00) |
| #define | UART5_BASE (APB1PERIPH_BASE + 0x5000) |
| #define | I2C1_BASE (APB1PERIPH_BASE + 0x5400) |
| #define | I2C2_BASE (APB1PERIPH_BASE + 0x5800) |
| #define | CAN1_BASE (APB1PERIPH_BASE + 0x6400) |
| #define | CAN2_BASE (APB1PERIPH_BASE + 0x6800) |
| #define | BKP_BASE (APB1PERIPH_BASE + 0x6C00) |
| #define | PWR_BASE (APB1PERIPH_BASE + 0x7000) |
| #define | DAC_BASE (APB1PERIPH_BASE + 0x7400) |
| #define | CEC_BASE (APB1PERIPH_BASE + 0x7800) |
| #define | AFIO_BASE (APB2PERIPH_BASE + 0x0000) |
| #define | EXTI_BASE (APB2PERIPH_BASE + 0x0400) |
| #define | GPIOA_BASE (APB2PERIPH_BASE + 0x0800) |
| #define | GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) |
| #define | GPIOC_BASE (APB2PERIPH_BASE + 0x1000) |
| #define | GPIOD_BASE (APB2PERIPH_BASE + 0x1400) |
| #define | GPIOE_BASE (APB2PERIPH_BASE + 0x1800) |
| #define | GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) |
| #define | GPIOG_BASE (APB2PERIPH_BASE + 0x2000) |
| #define | ADC1_BASE (APB2PERIPH_BASE + 0x2400) |
| #define | ADC2_BASE (APB2PERIPH_BASE + 0x2800) |
| #define | TIM1_BASE (APB2PERIPH_BASE + 0x2C00) |
| #define | SPI1_BASE (APB2PERIPH_BASE + 0x3000) |
| #define | TIM8_BASE (APB2PERIPH_BASE + 0x3400) |
| #define | USART1_BASE (APB2PERIPH_BASE + 0x3800) |
| #define | ADC3_BASE (APB2PERIPH_BASE + 0x3C00) |
| #define | TIM15_BASE (APB2PERIPH_BASE + 0x4000) |
| #define | TIM16_BASE (APB2PERIPH_BASE + 0x4400) |
| #define | TIM17_BASE (APB2PERIPH_BASE + 0x4800) |
| #define | TIM9_BASE (APB2PERIPH_BASE + 0x4C00) |
| #define | TIM10_BASE (APB2PERIPH_BASE + 0x5000) |
| #define | TIM11_BASE (APB2PERIPH_BASE + 0x5400) |
| #define | SDIO_BASE (PERIPH_BASE + 0x18000) |
| #define | DMA1_BASE (AHBPERIPH_BASE + 0x0000) |
| #define | DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) |
| #define | DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) |
| #define | DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) |
| #define | DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) |
| #define | DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) |
| #define | DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) |
| #define | DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) |
| #define | DMA2_BASE (AHBPERIPH_BASE + 0x0400) |
| #define | DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) |
| #define | DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) |
| #define | DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) |
| #define | DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) |
| #define | DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) |
| #define | RCC_BASE (AHBPERIPH_BASE + 0x1000) |
| #define | CRC_BASE (AHBPERIPH_BASE + 0x3000) |
| #define | FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) |
| #define | OB_BASE ((uint32_t)0x1FFFF800) |
| #define | ETH_BASE (AHBPERIPH_BASE + 0x8000) |
| #define | ETH_MAC_BASE (ETH_BASE) |
| #define | ETH_MMC_BASE (ETH_BASE + 0x0100) |
| #define | ETH_PTP_BASE (ETH_BASE + 0x0700) |
| #define | ETH_DMA_BASE (ETH_BASE + 0x1000) |
| #define | FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) |
| #define | FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) |
| #define | FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) |
| #define | FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) |
| #define | FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) |
| #define | DBGMCU_BASE ((uint32_t)0xE0042000) |
| #define ADC1_BASE (APB2PERIPH_BASE + 0x2400) |
Definition at line 1322 of file stm32f10x.h.
| #define ADC2_BASE (APB2PERIPH_BASE + 0x2800) |
Definition at line 1323 of file stm32f10x.h.
| #define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) |
Definition at line 1328 of file stm32f10x.h.
| #define AFIO_BASE (APB2PERIPH_BASE + 0x0000) |
Definition at line 1313 of file stm32f10x.h.
| #define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) |
Definition at line 1284 of file stm32f10x.h.
| #define APB1PERIPH_BASE PERIPH_BASE |
Definition at line 1282 of file stm32f10x.h.
| #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) |
Definition at line 1283 of file stm32f10x.h.
| #define BKP_BASE (APB1PERIPH_BASE + 0x6C00) |
Definition at line 1308 of file stm32f10x.h.
| #define CAN1_BASE (APB1PERIPH_BASE + 0x6400) |
Definition at line 1306 of file stm32f10x.h.
| #define CAN2_BASE (APB1PERIPH_BASE + 0x6800) |
Definition at line 1307 of file stm32f10x.h.
| #define CEC_BASE (APB1PERIPH_BASE + 0x7800) |
Definition at line 1311 of file stm32f10x.h.
| #define CRC_BASE (AHBPERIPH_BASE + 0x3000) |
Definition at line 1353 of file stm32f10x.h.
| #define DAC_BASE (APB1PERIPH_BASE + 0x7400) |
Definition at line 1310 of file stm32f10x.h.
| #define DBGMCU_BASE ((uint32_t)0xE0042000) |
Debug MCU registers base address
Definition at line 1370 of file stm32f10x.h.
| #define DMA1_BASE (AHBPERIPH_BASE + 0x0000) |
Definition at line 1338 of file stm32f10x.h.
| #define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) |
Definition at line 1339 of file stm32f10x.h.
| #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) |
Definition at line 1340 of file stm32f10x.h.
| #define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) |
Definition at line 1341 of file stm32f10x.h.
| #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) |
Definition at line 1342 of file stm32f10x.h.
| #define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) |
Definition at line 1343 of file stm32f10x.h.
| #define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) |
Definition at line 1344 of file stm32f10x.h.
| #define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) |
Definition at line 1345 of file stm32f10x.h.
| #define DMA2_BASE (AHBPERIPH_BASE + 0x0400) |
Definition at line 1346 of file stm32f10x.h.
| #define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) |
Definition at line 1347 of file stm32f10x.h.
| #define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) |
Definition at line 1348 of file stm32f10x.h.
| #define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) |
Definition at line 1349 of file stm32f10x.h.
| #define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) |
Definition at line 1350 of file stm32f10x.h.
| #define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) |
Definition at line 1351 of file stm32f10x.h.
| #define ETH_BASE (AHBPERIPH_BASE + 0x8000) |
Definition at line 1358 of file stm32f10x.h.
| #define ETH_DMA_BASE (ETH_BASE + 0x1000) |
Definition at line 1362 of file stm32f10x.h.
| #define ETH_MAC_BASE (ETH_BASE) |
Definition at line 1359 of file stm32f10x.h.
| #define ETH_MMC_BASE (ETH_BASE + 0x0100) |
Definition at line 1360 of file stm32f10x.h.
| #define ETH_PTP_BASE (ETH_BASE + 0x0700) |
Definition at line 1361 of file stm32f10x.h.
| #define EXTI_BASE (APB2PERIPH_BASE + 0x0400) |
Definition at line 1314 of file stm32f10x.h.
| #define FLASH_BASE ((uint32_t)0x08000000) |
FLASH base address in the alias region
Definition at line 1272 of file stm32f10x.h.
| #define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) |
Flash registers base address
Definition at line 1355 of file stm32f10x.h.
| #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) |
FSMC Bank1 registers base address
Definition at line 1364 of file stm32f10x.h.
| #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) |
FSMC Bank1E registers base address
Definition at line 1365 of file stm32f10x.h.
| #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) |
FSMC Bank2 registers base address
Definition at line 1366 of file stm32f10x.h.
| #define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) |
FSMC Bank3 registers base address
Definition at line 1367 of file stm32f10x.h.
| #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) |
FSMC Bank4 registers base address
Definition at line 1368 of file stm32f10x.h.
| #define FSMC_R_BASE ((uint32_t)0xA0000000) |
FSMC registers base address Peripheral memory map
Definition at line 1279 of file stm32f10x.h.
| #define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) |
Definition at line 1315 of file stm32f10x.h.
| #define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) |
Definition at line 1316 of file stm32f10x.h.
| #define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) |
Definition at line 1317 of file stm32f10x.h.
| #define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) |
Definition at line 1318 of file stm32f10x.h.
| #define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) |
Definition at line 1319 of file stm32f10x.h.
| #define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) |
Definition at line 1320 of file stm32f10x.h.
| #define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) |
Definition at line 1321 of file stm32f10x.h.
| #define I2C1_BASE (APB1PERIPH_BASE + 0x5400) |
Definition at line 1304 of file stm32f10x.h.
| #define I2C2_BASE (APB1PERIPH_BASE + 0x5800) |
Definition at line 1305 of file stm32f10x.h.
| #define IWDG_BASE (APB1PERIPH_BASE + 0x3000) |
Definition at line 1297 of file stm32f10x.h.
| #define OB_BASE ((uint32_t)0x1FFFF800) |
Flash Option Bytes base address
Definition at line 1356 of file stm32f10x.h.
| #define PERIPH_BASE ((uint32_t)0x40000000) |
Peripheral base address in the alias region
Definition at line 1274 of file stm32f10x.h.
| #define PERIPH_BB_BASE ((uint32_t)0x42000000) |
Peripheral base address in the bit-band region
Definition at line 1277 of file stm32f10x.h.
| #define PWR_BASE (APB1PERIPH_BASE + 0x7000) |
Definition at line 1309 of file stm32f10x.h.
| #define RCC_BASE (AHBPERIPH_BASE + 0x1000) |
Definition at line 1352 of file stm32f10x.h.
| #define RTC_BASE (APB1PERIPH_BASE + 0x2800) |
Definition at line 1295 of file stm32f10x.h.
| #define SDIO_BASE (PERIPH_BASE + 0x18000) |
Definition at line 1336 of file stm32f10x.h.
| #define SPI1_BASE (APB2PERIPH_BASE + 0x3000) |
Definition at line 1325 of file stm32f10x.h.
| #define SPI2_BASE (APB1PERIPH_BASE + 0x3800) |
Definition at line 1298 of file stm32f10x.h.
| #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) |
Definition at line 1299 of file stm32f10x.h.
| #define SRAM_BASE ((uint32_t)0x20000000) |
SRAM base address in the alias region
Definition at line 1273 of file stm32f10x.h.
| #define SRAM_BB_BASE ((uint32_t)0x22000000) |
SRAM base address in the bit-band region
Definition at line 1276 of file stm32f10x.h.
| #define TIM10_BASE (APB2PERIPH_BASE + 0x5000) |
Definition at line 1333 of file stm32f10x.h.
| #define TIM11_BASE (APB2PERIPH_BASE + 0x5400) |
Definition at line 1334 of file stm32f10x.h.
| #define TIM12_BASE (APB1PERIPH_BASE + 0x1800) |
Definition at line 1292 of file stm32f10x.h.
| #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) |
Definition at line 1293 of file stm32f10x.h.
| #define TIM14_BASE (APB1PERIPH_BASE + 0x2000) |
Definition at line 1294 of file stm32f10x.h.
| #define TIM15_BASE (APB2PERIPH_BASE + 0x4000) |
Definition at line 1329 of file stm32f10x.h.
| #define TIM16_BASE (APB2PERIPH_BASE + 0x4400) |
Definition at line 1330 of file stm32f10x.h.
| #define TIM17_BASE (APB2PERIPH_BASE + 0x4800) |
Definition at line 1331 of file stm32f10x.h.
| #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) |
Definition at line 1324 of file stm32f10x.h.
| #define TIM2_BASE (APB1PERIPH_BASE + 0x0000) |
Definition at line 1286 of file stm32f10x.h.
| #define TIM3_BASE (APB1PERIPH_BASE + 0x0400) |
Definition at line 1287 of file stm32f10x.h.
| #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) |
Definition at line 1288 of file stm32f10x.h.
| #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) |
Definition at line 1289 of file stm32f10x.h.
| #define TIM6_BASE (APB1PERIPH_BASE + 0x1000) |
Definition at line 1290 of file stm32f10x.h.
| #define TIM7_BASE (APB1PERIPH_BASE + 0x1400) |
Definition at line 1291 of file stm32f10x.h.
| #define TIM8_BASE (APB2PERIPH_BASE + 0x3400) |
Definition at line 1326 of file stm32f10x.h.
| #define TIM9_BASE (APB2PERIPH_BASE + 0x4C00) |
Definition at line 1332 of file stm32f10x.h.
| #define UART4_BASE (APB1PERIPH_BASE + 0x4C00) |
Definition at line 1302 of file stm32f10x.h.
| #define UART5_BASE (APB1PERIPH_BASE + 0x5000) |
Definition at line 1303 of file stm32f10x.h.
| #define USART1_BASE (APB2PERIPH_BASE + 0x3800) |
Definition at line 1327 of file stm32f10x.h.
| #define USART2_BASE (APB1PERIPH_BASE + 0x4400) |
Definition at line 1300 of file stm32f10x.h.
| #define USART3_BASE (APB1PERIPH_BASE + 0x4800) |
Definition at line 1301 of file stm32f10x.h.
| #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) |
Definition at line 1296 of file stm32f10x.h.
1.7.5 
