#include <core_cm3.h>

Field Documentation

__IO uint32_t IABR[8]

Offset: 0x200 Interrupt Active bit Register

Definition at line 142 of file core_cm3.h.

__IO uint32_t ICER[8]

Offset: 0x080 Interrupt Clear Enable Register

Definition at line 136 of file core_cm3.h.

__IO uint32_t ICPR[8]

Offset: 0x180 Interrupt Clear Pending Register

Definition at line 140 of file core_cm3.h.

__IO uint8_t IP[240]

Offset: 0x300 Interrupt Priority Register (8Bit wide)

Definition at line 144 of file core_cm3.h.

__IO uint32_t ISER[8]

Offset: 0x000 Interrupt Set Enable Register

Definition at line 134 of file core_cm3.h.

__IO uint32_t ISPR[8]

Offset: 0x100 Interrupt Set Pending Register

Definition at line 138 of file core_cm3.h.

uint32_t RESERVED0[24]

Definition at line 135 of file core_cm3.h.

uint32_t RESERVED2[24]

Definition at line 139 of file core_cm3.h.

uint32_t RESERVED3[24]

Definition at line 141 of file core_cm3.h.

uint32_t RESERVED4[56]

Definition at line 143 of file core_cm3.h.

uint32_t RESERVED5[644]

Definition at line 145 of file core_cm3.h.

uint32_t RSERVED1[24]

Definition at line 137 of file core_cm3.h.

__O uint32_t STIR

Offset: 0xE00 Software Trigger Interrupt Register

Definition at line 146 of file core_cm3.h.

The documentation for this struct was generated from the following file:

Data Fields