ITM_Type Struct Reference

#include <core_cm3.h>

Data Fields
union {
__O uint8_t   u8
__O uint16_t   u16
__O uint32_t   u32
}	PORT [32]
uint32_t	RESERVED0 [864]
__IO uint32_t	TER
uint32_t	RESERVED1 [15]
__IO uint32_t	TPR
uint32_t	RESERVED2 [15]
__IO uint32_t	TCR
uint32_t	RESERVED3 [29]
__IO uint32_t	IWR
__IO uint32_t	IRR
__IO uint32_t	IMCR
uint32_t	RESERVED4 [43]
__IO uint32_t	LAR
__IO uint32_t	LSR
uint32_t	RESERVED5 [6]
__I uint32_t	PID4
__I uint32_t	PID5
__I uint32_t	PID6
__I uint32_t	PID7
__I uint32_t	PID0
__I uint32_t	PID1
__I uint32_t	PID2
__I uint32_t	PID3
__I uint32_t	CID0
__I uint32_t	CID1
__I uint32_t	CID2
__I uint32_t	CID3

---

Field Documentation

__I uint32_t CID0

Offset: ITM Component Identification Register #0

Definition at line 440 of file core_cm3.h.

__I uint32_t CID1

Offset: ITM Component Identification Register #1

Definition at line 441 of file core_cm3.h.

__I uint32_t CID2

Offset: ITM Component Identification Register #2

Definition at line 442 of file core_cm3.h.

__I uint32_t CID3

Offset: ITM Component Identification Register #3

Definition at line 443 of file core_cm3.h.

__IO uint32_t IMCR

Offset: ITM Integration Mode Control Register

Definition at line 427 of file core_cm3.h.

__IO uint32_t IRR

Offset: ITM Integration Read Register

Definition at line 426 of file core_cm3.h.

__IO uint32_t IWR

Offset: ITM Integration Write Register

Definition at line 425 of file core_cm3.h.

__IO uint32_t LAR

Offset: ITM Lock Access Register

Definition at line 429 of file core_cm3.h.

__IO uint32_t LSR

Offset: ITM Lock Status Register

Definition at line 430 of file core_cm3.h.

__I uint32_t PID0

Offset: ITM Peripheral Identification Register #0

Definition at line 436 of file core_cm3.h.

__I uint32_t PID1

Offset: ITM Peripheral Identification Register #1

Definition at line 437 of file core_cm3.h.

__I uint32_t PID2

Offset: ITM Peripheral Identification Register #2

Definition at line 438 of file core_cm3.h.

__I uint32_t PID3

Offset: ITM Peripheral Identification Register #3

Definition at line 439 of file core_cm3.h.

__I uint32_t PID4

Offset: ITM Peripheral Identification Register #4

Definition at line 432 of file core_cm3.h.

__I uint32_t PID5

Offset: ITM Peripheral Identification Register #5

Definition at line 433 of file core_cm3.h.

__I uint32_t PID6

Offset: ITM Peripheral Identification Register #6

Definition at line 434 of file core_cm3.h.

__I uint32_t PID7

Offset: ITM Peripheral Identification Register #7

Definition at line 435 of file core_cm3.h.

__O { ... } PORT[32]

Offset: 0x00 ITM Stimulus Port Registers

uint32_t RESERVED0[864]

Definition at line 418 of file core_cm3.h.

uint32_t RESERVED1[15]

Definition at line 420 of file core_cm3.h.

uint32_t RESERVED2[15]

Definition at line 422 of file core_cm3.h.

uint32_t RESERVED3[29]

Definition at line 424 of file core_cm3.h.

uint32_t RESERVED4[43]

Definition at line 428 of file core_cm3.h.

uint32_t RESERVED5[6]

Definition at line 431 of file core_cm3.h.

__IO uint32_t TCR

Offset: ITM Trace Control Register

Definition at line 423 of file core_cm3.h.

__IO uint32_t TER

Offset: ITM Trace Enable Register

Definition at line 419 of file core_cm3.h.

__IO uint32_t TPR

Offset: ITM Trace Privilege Register

Definition at line 421 of file core_cm3.h.

__O uint16_t u16

Offset: ITM Stimulus Port 16-bit

Definition at line 415 of file core_cm3.h.

__O uint32_t u32

Offset: ITM Stimulus Port 32-bit

Definition at line 416 of file core_cm3.h.

__O uint8_t u8

Offset: ITM Stimulus Port 8-bit

Definition at line 414 of file core_cm3.h.

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The documentation for this struct was generated from the following file:

• /opt/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/CoreSupport/core_cm3.h