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    STM32F10x Standard Peripherals Library
    3.5.0
    
   
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Defines | |
| #define | PWR_OFFSET (PWR_BASE - PERIPH_BASE) | 
| #define | CR_OFFSET (PWR_OFFSET + 0x00) | 
| #define | DBP_BitNumber 0x08 | 
| #define | CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) | 
| #define | PVDE_BitNumber 0x04 | 
| #define | CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) | 
| #define | CSR_OFFSET (PWR_OFFSET + 0x04) | 
| #define | EWUP_BitNumber 0x08 | 
| #define | CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) | 
| #define | CR_DS_MASK ((uint32_t)0xFFFFFFFC) | 
| #define | CR_PLS_MASK ((uint32_t)0xFFFFFF1F) | 
| #define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) | 
Definition at line 55 of file stm32f10x_pwr.c.
| #define CR_DS_MASK ((uint32_t)0xFFFFFFFC) | 
Definition at line 71 of file stm32f10x_pwr.c.
| #define CR_OFFSET (PWR_OFFSET + 0x00) | 
Definition at line 53 of file stm32f10x_pwr.c.
| #define CR_PLS_MASK ((uint32_t)0xFFFFFF1F) | 
Definition at line 72 of file stm32f10x_pwr.c.
| #define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) | 
Definition at line 59 of file stm32f10x_pwr.c.
| #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) | 
Definition at line 66 of file stm32f10x_pwr.c.
| #define CSR_OFFSET (PWR_OFFSET + 0x04) | 
Definition at line 64 of file stm32f10x_pwr.c.
| #define DBP_BitNumber 0x08 | 
Definition at line 54 of file stm32f10x_pwr.c.
| #define EWUP_BitNumber 0x08 | 
Definition at line 65 of file stm32f10x_pwr.c.
| #define PVDE_BitNumber 0x04 | 
Definition at line 58 of file stm32f10x_pwr.c.
| #define PWR_OFFSET (PWR_BASE - PERIPH_BASE) | 
Definition at line 48 of file stm32f10x_pwr.c.